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ksz8842-pmql/pmbl 2-port ethernet switch with pci interface rev.1.5 linkmd is a registered trademark of micrel, inc magic packet is a trademark of advanced micro devices, inc. product/application names used in this datas heet are for identification purposes only and may be trademarks of their respective companies. micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? te l +1 (408) 944-0800 ? fax + 1 (408) 474-1000 ? http://www.micre l.com october 2007 m9999-100207-1. 5 general description the ksz8842-series of 2-port switches includes pci and non-pci cpu interfaces. this datasheet describes the ksz8842-pmql/pmbl pci cpu interface chips. ksz8842-pmql is pqfp package chip, KSZ8842-PMBL is lfbga package chip. for information on the ksz8842-mql/mbl cpu non-pci interface switches, refer to the ksz8842-mql/mbl datasheet. the ksz8842-pmql/pmbl is the industry?s first fully managed 2-port switch with a 32 bit/33mhz pci processor interface. it is a proven, 4th generation, integrated layer 2 switch that is compliant with the ieee 802.3u standard. an industrial temperature grade version of the ksz8842-pmql/pmbl, also can be ordered the ksz8842-pmqli/pmbl am. the ksz8842-pmql/pmbl can be configured as a switch or as a low-latency (<310 nanoseconds) repeater in latency-critical, embedded or industrial ethernet applications. for industrial automation applications, the linkmd ? ksz8842-pmql/pmbl can run in half-duplex mode regardless of the application. the ksz8842-pmql/pmbl offers an extensive feature set that includes tag/port- based vlan, quality of service (qos) priority management, management information base (mib) counters, and cpu control/data interfaces to effectively address fast ethernet applications. the ksz8842-pmql/pmbl contains two 10/100 transceivers with patented, mixed-signal, low-power technology three media access control (mac) units, a direct memory access (d ma) channel, a high-speed, non-blocking, switch fabr ic, a dedicated 1k entry forwarding table, and an on-chip frame buffer memory . datasheets and support documentation can be found on micrel?s web site at: www.micrel.com . functional diagram figure 1. ksz8842-pmql/pmbl functional diagram
micrel, inc. ksz8842-pmql/pmbl october 2007 2 m9999-100207-1. 5 features switch management ? non-blocking switch fabric assures fast packet delivery by utilizing a 1k entry mac address look- up engine and a store-and-forward architecture ? fully compliant with ieee802.3u standards ? full-duplex ieee 802.3x flow control (pause) with force mode option ? half-duplex back pres sure flow control advanced switch management ? ieee 802.1q vlan support for up to 16 groups (full- range of vlan ids) ? vlan id tag/untag options, per port basis ? ieee 802.1p/q tag insertion or removal on a per-port basis (egress) ? programmable rate limiting at the ingress and egress port ? broadcast storm protection ? ieee 802.1d spanning tree protocol support ? mac filtering function to filter unicast packets ? unknown mac address forwarding function ? direct forwarding mode enabling the processor to identify the ingress port and to specify the egress port ? igmp v1/v2 snooping support for multicast packet filtering ? ipv6 multicast listener discovery (mld) snooping support monitoring ? port mirroring/monitoring/s niffing: ingress and/or egress traffic to any port ? management information base (mib) counters for fully compliant statistics gatheri ng: 32 mib counters per port ? loop back modes for remote failure diagnostics comprehensive register access ? there are three kinds of register groups: ? the pci configuration registers are used to initialize and configure the pci interface ? the pci control/status registers are used to communicate between the host and ksz8842- pmql/pmbl ? switch registers are used to support transceiver control and status. they are confi gurable on-the-fly (port- priority, 802.1p/d/q, etc.) qos/cos packets prioritization support ? per port, 802.1p and diffserv based ? re-mapping of 802.1p priority field on a per port basis power modes, packaging, and power supplies ? full-chip hardware power-do wn (register configuration not saved) provides for low power dissipation ? per port-based software power-save on phy (idle link detection, register conf iguration preserved) ? single power supply: 3.3v ? commercial temperature range: 0c to +70c ? industrial temperature range: ?40c to +85c ? available in 128-pin pqfp and 100-ball lfbga additional features in addition to offering all of the features of an integrated layer-2 managed switch, the ksz8842-pmql/pmbl offers: ? repeater mode ca pabilities to allow for cut through in latency critical industrial ethernet or embedded ethernet applications ? dynamic buffer memory scheme essential for applications such as video over ip where image jitter is unacceptable ? 2-port switch with a 32-bit/33mhz pci processor interface. ? micrel linkmd ? cable diagnostics to determine cable length, diagnose faulty cables, and determine distance- to-fault ? hewlett packard (hp) au to mdi-x crossover with disable and enable options ? four priority queues to handle voice, video, data, and control packets ? ability to transmit and receive jumbo frame sizes up to 1916 bytes applications ? video distribution systems ? high-end cable, satellite, and ip set-top boxes ? video over ip ? voice over ip (voip) and analog telephone adapters (ata) ? industrial control in latency critical applications ? motion control ? industrial control sensor devices (temperature, pressure, levels, and valves) ? security and surveillance cameras markets ? fast ethernet ? embedded ethernet ? industrial ethernet
micrel, inc. ksz8842-pmql/pmbl october 2007 3 m9999-100207-1. 5 ordering information part number operation temp. range package ksz8842-pmql 0 o c to 70 o c 128-pin pqfp ksz8842-pmqli (industrial grade) -40 o c to +85 o c 128-pin pqfp KSZ8842-PMBL 0 o c to 70 o c 100-ball lfbga KSZ8842-PMBL am (industrial/automotive grade) -40 o c to +85 o c 100-ball lfbga revision history revision date summary of changes 1.0 09/29/05 data sheet created. 1.1 01/13/06 package information updated. 1.2 01/16/07 update support transformer, table and other. 1.3 04/17/07 add the base address and range for host mib, change description for soft reset and other. 1.4 06/01/07 add the package thermal inf ormation in the operating ratings. 1.5 10/02/07 add the ksz8842-pm bl bga device information.
micrel, inc. ksz8842-pmql/pmbl october 2007 4 m9999-100207-1. 5 contents pin confi guration .............................................................................................................. ................................................ 9 pins description of ksz8842-pmql............................................................................................... ............................... 11 functional d escripti on ......................................................................................................... .......................................... 20 functional overview: pc i bus interf ace unit.................................................................................... ........................... 20 pci bus in terface.............................................................................................................. ............................................ 20 txdma logic and tx buffer ma nager .............................................................................................. ........................... 20 rxdma logic and rx buffer m anager .............................................................................................. .......................... 20 functional overview: physical layer transc eiver (phy) .......................................................................... ................. 20 100base-tx tr ansmit............................................................................................................ ...................................... 20 100base-tx re ceive............................................................................................................. ...................................... 20 pll clock synthesizer (recovery) ............................................................................................... ................................ 21 scrambler/de-scrambler (100base-tx only)....................................................................................... ....................... 21 10base-t tr ansmit .............................................................................................................. ........................................ 21 10base-t re ceive ............................................................................................................... ........................................ 21 power mana gement............................................................................................................... ....................................... 21 mdi/mdi-x auto crossover ....................................................................................................... ................................... 21 straight cable................................................................................................................. ...................................... 22 crossover cable................................................................................................................ ................................... 23 auto nego tiation ............................................................................................................... ............................................ 23 linkmd cable diagnostics....................................................................................................... ..................................... 24 access......................................................................................................................... ......................................... 24 usage .......................................................................................................................... ......................................... 25 functional overview : mac and switch............................................................................................ ............................. 25 address lookup ................................................................................................................. ........................................... 25 learning ....................................................................................................................... ................................................. 25 migration ...................................................................................................................... ................................................. 25 aging .......................................................................................................................... ................................................... 25 forwarding ..................................................................................................................... ............................................... 26 switching engine ............................................................................................................... ........................................... 27 mac operation .................................................................................................................. ........................................... 28 inter packet gap (i pg) ......................................................................................................... ........................................ 28 back-off al gorithm............................................................................................................. ........................................... 28 late collision ................................................................................................................. ............................................... 28 illegal pack et si ze............................................................................................................ ............................................. 28 flow c ontrol................................................................................................................... ............................................... 28 half-duplex ba ckpressure ....................................................................................................... ..................................... 28 broadcast stor m protection ..................................................................................................... ..................................... 29 repeater mode .................................................................................................................. ........................................... 29 clock generator................................................................................................................ ............................................ 29 advanced swit ch funct ions ...................................................................................................... .................................... 29 spanning tree suppo rt.......................................................................................................... ....................................... 29 igmp s upport ................................................................................................................... ............................................ 30 ?igmp? snoopi ng................................................................................................................ .................................. 30 ?multicast address insertion? in the static mac table.......................................................................... ............... 30 ipv6 mld snooping .............................................................................................................. ........................................ 30 port mirror ing support......................................................................................................... .......................................... 30 ieee 802.1q vlan support ....................................................................................................... .................................. 31 qos priority suppo rt ........................................................................................................... .......................................... 31 port-based priority............................................................................................................ ............................................ 31 802.1p-based priori ty .......................................................................................................... ......................................... 32 diffserv based prio rity ........................................................................................................ .......................................... 32 rate limiti ng s upport .......................................................................................................... ......................................... 32 mac filteri ng function ......................................................................................................... ........................................ 33
micrel, inc. ksz8842-pmql/pmbl october 2007 5 m9999-100207-1. 5 configuration interf ace........................................................................................................ .......................................... 33 eeprom interface ............................................................................................................... ........................................ 33 loop back support.............................................................................................................. .......................................... 33 host comm unicatio n ............................................................................................................. ......................................... 35 host communication descripto r lists and data buffers ........................................................................... ................... 35 receive descriptors (rdes0-rdes3) .............................................................................................. ........................... 35 transmit descriptor s (tdes0-tdes3)............................................................................................. ............................ 37 pci configurati on registers .................................................................................................... ...................................... 39 configuration id regist er (cfid offset 00h) .................................................................................... ........................... 39 command and status configuration register (cfcs offset 04h).................................................................... ........... 39 configuration revision regi ster (cfrv o ffset 08h).............................................................................. ...................... 41 configuration latency timer r egister (cflt offset 0ch)......................................................................... .................. 41 configuration base memory addres s register (cbm a offset 10h) ................................................................... ......... 42 subsystem id register (csid offset 2ch) ........................................................................................ .......................... 42 configuration interrupt regi ster (cfit of fset 3ch) ............................................................................. ........................ 42 pci control & stat us registers ................................................................................................. .................................... 43 mac dma transmit control regist er (mdtxc o ffset 0x0000) ........................................................................ ........... 43 mac dma receive control regist er (mdrxc o ffset 0x0004)......................................................................... ........... 44 mac dma transmit start command regi ster (mdtsc o ffset 0x0008) .................................................................. ... 45 mac dma receive start command r egister (mdrsc o ffset 0x 000c) ................................................................... .. 46 transmit descriptor list base ad dress register (t dlb offset 0x0010)............................................................ .......... 46 receive descriptor list base addr ess register (rdl b offset 0x0014) ............................................................. ......... 46 reserved (off set 0x 0018)....................................................................................................... ...................................... 46 reserved (off set 0x001c) ....................................................................................................... ..................................... 46 mac multicast table 0 regist er (mtr0 offs et 0x0020) ............................................................................ .................. 46 mac multicast table 1 regist er (mtr1 offs et 0x0024) ............................................................................ .................. 47 interrupt enable register (inten offs et 0x0028) ................................................................................ ........................ 47 interrupt status register (intst offs et 0x002c) ................................................................................ ......................... 48 mac additional station addres s low register (maal0-15) ......................................................................... ............... 49 mac additional station addres s high register (maah0-15)........................................................................ ............... 49 mac/phy and cont rol registers .................................................................................................. ................................. 50 mac address register low (0x0200): marl ........................................................................................ ...................... 50 mac address register middle (0x020 2): marm ..................................................................................... .................... 50 mac address register high (0x0204 ): marh ....................................................................................... ...................... 50 reserved (offse t 0x0206 - 0x020a ............................................................................................... ............................... 51 on-chip bus control regist er (offset 0x 0210): obcr............................................................................. ................... 51 eeprom control register (offset 0x02 12): eepcr................................................................................. .................. 51 memory bist info regist er (offset 0x 0214): mbir ................................................................................ ..................... 52 global reset register (offset 0x021 6): grr..................................................................................... .......................... 52 switch re gisters ............................................................................................................... .............................................. 52 switch id and enable regist er (offset 0x 0400): sider ........................................................................... ................... 52 switch global control register 1 (offset 0x 0402): sg cr1 ........................................................................ ................. 53 switch global control register 2 (offset 0x 0404): sg cr2 ........................................................................ ................. 54 switch global control register 3 (offset 0x 0406): sg cr3 ........................................................................ ................. 55 switch global control register 4 (offset 0x 0408): sg cr4 ........................................................................ ................. 56 switch global control register 5 (offset 0x 040a): sg cr5 ........................................................................ ................. 56 switch global control register 6 (offset 0x 0410): sg cr6 ........................................................................ ................. 57 switch global control regi ster 7 (0x041 2): sgcr7 ............................................................................... ..................... 58 reserved (offset 0x0414 - 0x 046f) .............................................................................................. ............................... 58 mac address register 1 (offset 0x047 0): macar1 ................................................................................. .................. 58 mac address register 2 (offset 0x047 2): macar2 ................................................................................. .................. 58 mac address register 3 (offset 0x047 4): macar3 ................................................................................. .................. 58 reserved (offset 0x0476 - 0x 047f) .............................................................................................. ............................... 58 priority control register 1 (offset 0x0 480): tosr1............................................................................. ........................ 59 tos priority control regist er 2 (offset 0x482): tosr2 .......................................................................... .................... 59 tos priority control regist er 3 (offset 0x484): tosr3 .......................................................................... .................... 60
micrel, inc. ksz8842-pmql/pmbl october 2007 6 m9999-100207-1. 5 tos priority control regist er 4 (offset 0x486): tosr4 .......................................................................... .................... 60 tos priority control regist er 5 (offset 0x488): tosr5 .......................................................................... .................... 61 tos priority control register 6 (offset 0x 48a): tosr6.......................................................................... .................... 62 tos priority control regist er 7 (offset 0x490): tosr7 .......................................................................... .................... 62 tos priority control regist er 8 (offset 0x492): tosr8 .......................................................................... .................... 63 reserved (offset 0x0494 - 0x 049a) .............................................................................................. ............................... 63 indirect access control regi ster (offset 0x04a0): iacr ......................................................................... .................... 64 indirect access data register 1 (offset 0x 04a2): iadr1 ......................................................................... ................... 64 indirect access data register 2 (offset 0x 04a4): iadr2 ......................................................................... ................... 64 indirect access data register 3 (offset 0x 04a6): iadr3 ......................................................................... ................... 64 indirect access data register 4 (offset 0x 04a8): iadr4 ......................................................................... ................... 64 indirect access data regist er 5 (offset 0x04aa): iadr5 ......................................................................... ................... 65 reserved (offset 0x04b0 - 0x04ba) .............................................................................................. .............................. 65 reserved (offset 0x04c0 ?0x04cf) ............................................................................................... ............................. 65 phy 1 mii basic control regist er (offset 0x 04d0): p1 mbcr ....................................................................... .............. 65 phy 1 mii basic status regist er (offset 0x 04d2): p1mbsr........................................................................ ............... 66 phy 1 phyid low register (offset 0x04d4) : phy1ilr.............................................................................. ................ 67 phy 1 phyid high register (offset 0x04d 6): phy1ihr ........................................................................... ............... 67 phy 1 auto-negotiation advertisement register (offset 0x04d8): p1anar .......................................................... .... 67 phy 1 auto-negotiation link partner abilit y register (offset 0x04da): p1 anlpr.................................................. ... 68 phy 2 mii basic control regist er (offset 0x 04e0): p2 mbcr ....................................................................... .............. 68 phy 2 mii basic status regist er (offset 0x 04e2): p2mbsr........................................................................ ............... 69 phy 2 phyid low register (offset 0x04e4) : phy2ilr .............................................................................. ................ 70 phy 2 phyid high register (offset 0x04e6) : phy2ihr............................................................................. ................ 70 phy 2 auto-negotiation advertisement register (offset 0x04e8): p2anar .......................................................... .... 70 phy 2 auto-negotiation link partner abilit y register (offset 0x04ea): p2 anlpr.................................................. ... 71 phy1 linkmd control/status (offset 0x04f 0): p1vct.............................................................................. .................. 72 phy1 special control/status regi ster (offset 0x04f2): p1phyctrl............................................................... ........ 72 phy2 linkmd control/status (offset 0x04f 4): p2vct.............................................................................. .................. 73 phy2 special control/status regi ster (offset 0x04f 6): p2phyctrl................................................................ ........ 73 reserved (offset 0x04f8 - 0x04fa).............................................................................................. ............................... 73 port 1 control register 1 (offset 0x050 0): p1cr1............................................................................... ........................ 74 port 1 control register 2 (offset 0x050 2): p1cr2............................................................................... ........................ 75 port 1 vid control register (offset 0x0504 ): p1 vidcr........................................................................... .................... 76 port 1 control register 3 (offset 0x050 6): p1cr3............................................................................... ........................ 76 port 1 ingress rate control r egister (offset 0x0508): p1ircr................................................................... ................ 77 port 1 egress rate control r egister (offset 0x050a): p1ercr .................................................................... ............. 79 port 1 phy special control/status, linkmd (offset 0x 0510): p1 scslmd ............................................................ ..... 81 port 1 control register 4 (offset 0x051 2): p1cr4............................................................................... ........................ 82 port 1 status register (offset 0x 0514): p1sr ................................................................................... .......................... 83 port 1 reserved (offs et 0x0516 ? 0x051a)....................................................................................... ........................... 84 port 2 control register 1 (offset 0x052 0): p2cr1............................................................................... ........................ 84 port 2 control register 2 (offset 0x052 2): p2cr2............................................................................... ........................ 85 port 2 vid control register (offset 0x0524 ): p2 vidcr........................................................................... .................... 86 port 2 control register 3 (offset 0x052 6): p2cr3............................................................................... ........................ 87 port 2 ingress rate control r egister (offset 0x0528): p2ircr................................................................... ................ 87 port 2 egress rate control r egister (offset 0x052a): p2ercr .................................................................... ............. 89 port 2 phy special control/status, linkmd (offset 0x 0530): p2 scslmd ............................................................ ..... 92 port 2 control register 4 (offset 0x053 2): p2cr4............................................................................... ........................ 92 port 2 status register (offset 0x 0534): p2sr ................................................................................... .......................... 94 port 2 reserved (offs et 0x0536 ? 0x053a)....................................................................................... ........................... 95 host control register 1 (offset 0x0540 ): p3cr1 ................................................................................. ........................ 95 host control register 2 (offset 0x0542 ): p3cr2 ................................................................................. ........................ 96 host vid control register (offset 0x0544) : p3vidcr............................................................................. .................... 97 host control register 3 (offset 0x0546 ): p3cr3 ................................................................................. ........................ 97 host ingress rate control regi ster (offset 0x 0548): p3ircr..................................................................... ................ 98
micrel, inc. ksz8842-pmql/pmbl october 2007 7 m9999-100207-1. 5 host egress rate control regi ster (offset 0x 054a): p3 ercr...................................................................... ............ 100 reserved (off set 0x 0550)....................................................................................................... .................................... 102 reserved (off set 0x 0554)....................................................................................................... .................................... 102 reserved (off set 0x 0556)....................................................................................................... .................................... 102 reserved (off set 0x 0560)....................................................................................................... .................................... 102 mib (management inform ation base) counters..................................................................................... .................... 103 additional mib informat ion..................................................................................................... ..................................... 105 static mac a ddress ta ble ....................................................................................................... .................................... 106 dynamic mac ad dress ta ble ...................................................................................................... ................................ 107 vlan table ..................................................................................................................... ............................................... 108 absolute maximum ratings (1) ............................................................................................................................... ....... 109 operating ratings (2) ............................................................................................................................... ....................... 109 electrical characteristics (4) ............................................................................................................................... ........... 109 timing di agrams ................................................................................................................ ........................................... 111 eeprom ti ming.................................................................................................................. ....................................... 111 auto negotiat ion ti ming........................................................................................................ ...................................... 112 reset timing................................................................................................................... ............................................ 113 selection of isolat ion transf ormers............................................................................................ ................................ 114 selection of refe rence crystal ................................................................................................. ................................... 114 package info rmation ............................................................................................................ ......................................... 115 acronyms a nd glo ssary.......................................................................................................... ..................................... 117
micrel, inc. ksz8842-pmql/pmbl october 2007 8 m9999-100207-1. 5 list of figures figure 1. ksz8842-pmql/pm bl functional diagr am ................................................................................. ...................... 1 figure 2. ksz8842-pmql 128- pin pqfp (t op view)................................................................................. ....................... 9 figure 3. KSZ8842-PMBL 100-ball lfbga (top vi ew) .............................................................................. .................... 10 figure 4. typical stra ight cable connection ................................................................................... ................................ 22 figure 5. typical cros sover cable connection .................................................................................. ............................. 23 figure 6. auto negotiatio n and parallel operation ............................................................................. ............................. 24 figure 7. destination addres s lookup flow chart, st age 1 ...................................................................... ...................... 26 figure 8. destinati on address resolution flow char t, stage 2.................................................................. ..................... 27 figure 9. 802.1p prio rity fiel d format........................................................................................ ...................................... 32 figure 10. port 2 fa r-end loop ba ck path ...................................................................................... ................................ 34 figure 11. port 1 and port 2 n ear-end (remote) loop back path ................................................................. ................. 34 figure 12. eeprom read cycle timing diagram ................................................................................... ..................... 111 figure 13. auto-n egotiation timing ............................................................................................ ................................... 112 figure 14. re set timing ....................................................................................................... .......................................... 113 figure 15. standard pa ckage: 128-p in pqfp ..................................................................................... .......................... 115 figure 16. standard pack age: 100-bal l lfbga .................................................................................... ......................... 116 list of tables table 1. ksz8842-pmq l pin descr iption.......................................................................................... ............................... 15 table 2. ksz8842-pmb l pin descr iption .......................................................................................... ............................... 19 table 3. mdi/mdi- x pin defi nitions ............................................................................................ ..................................... 22 table 4. ksz8841-pmql/ pmbl eeprom form at...................................................................................... ................... 30 table 5. fid+da lo okup in vlan mode ........................................................................................... .............................. 31 table 6. fid+sa loo kup in vlan mode ........................................................................................... .............................. 31 table 7. eepr om format ........................................................................................................ ....................................... 33 table 8. format of pe r port mib counter s....................................................................................... ............................... 103 table 9. port 1s ?per port? mib counters indirect memory offsets.............................................................. ................. 104 table 10. ?all port dropped packet? mib c ounters fo rmat........................................................................ .................... 104 table 11. ?all port dro pped packet? mib counters in direct memory offsets....................................................... .......... 104 table 12. static mac tabl e format (8 entries) .................................................................................. ............................ 106 table 13. dynamic mac address table format ( 1024 entries)...................................................................... ............... 107 table 14. vlan table format (16 entries)....................................................................................... .............................. 108 table 15. eeprom ti ming parameters ............................................................................................ ............................ 111 table 16. auto negot iation parameters ......................................................................................... ................................ 112 table 17. reset timing para meters ............................................................................................. ................................. 113 table 18. transformer selection criteria ...................................................................................... ................................. 114 table 19. qualified single port magnetics ..................................................................................... ................................ 114 table 20. typical reference crystal characteristics ............................................................................ .......................... 114
micrel, inc. ksz8842-pmql/pmbl october 2007 9 m9999-100207-1. 5 pin configuration figure 2. ksz8842-pmql 128-pin pqfp (top view)
micrel, inc. ksz8842-pmql/pmbl october 2007 10 m9999-100207-1. 5 balls configuration figure 3. KSZ8842-PMBL 100-ball lfbga (top view)
micrel, inc. ksz8842-pmql/pmbl october 2007 11 m9999-100207-1. 5 pins description of ksz8842-pmql pin number pin name type pin function 1 test_en i test enable for normal operation, pull-down this pin to ground. 2 scan_en i scan test scan mux enable for normal operation, pull-down this pin to ground. 3 4 5 6 7 8 p1led2 p1led1 p1led0 p2led2 p2led1 p2led0 opu opu opu opu opu opu port 1 and port 2 led indicators 1 defined as follows: leds turn on when low. chip global control register 5: sgcr5 bit [15,9] [0,0] default [0,1] p1led3 2 /p2led3 ? ? p1led2/p2led2 link/act 100link/act p1led1/p2led1 full duplex/col 10link/act p1led0/p2led0 speed full duplex reg. sgcr5 bit [15,9] [1,0] [1,1] p1led3 2 /p2led3 act ? p1led2/p2led2 link ? p1led1/p2led1 full duplex/col ? p1led0/p2led0 speed ? notes : 1. link = on; activity = blink; link/act = on/blink; full dup/col = on/blink; full duplex = on (full duplex); off (half duplex) speed = on (100base-t); off (10base-t) 2. p1led3 is pin 27. p2led3 is pin 22 port 1 and port 2 led indicators 1 for repeater mode defined as follows: switch global control register 5: sgcr5 bit [15,9] [0,0] default [0,1] [1,0],[1,1] p1led3/p2led3 rpt_col, rpt_act ? p1led2/p2led2 rpt_link3/rx, rpt_err3 ? p1led1/p2led1 rpt_link2/rx, rpt_err2 ? p1led0/p2led0 rpt_link1/rx, rpt_err1 ? note : 1. rpt_col = blink; rpt_link3/rx (host port) = on/blink; rpt_link2/rx (port 2) = on/blink; rpt_link1/rx (port 1) = on/blink; rpt_act = on if any activity; rpt_err3 (host port) = on if any crc error; rpt_err2 (port 2) = on if any crc error; rpt_err1 (port 1) = on if any crc error; 9 dgnd gnd digital ground 10 vddio p 3.3v digital i/o v dd
micrel, inc. ksz8842-pmql/pmbl october 2007 12 m9999-100207-1. 5 pin number pin name type pin function 11 nc ? no connect 12 pclk ipd pci bus clock this clock provides the timing for all pci bus phases. the rising edge defines the start of each phase. the clock maximum frequency is 33mhz. 13 nc ? no connect 14 nc ? no connect 15 nc ? no connect 16 intrn opd interrupt request active low signal to host cpu to request an interrupt when any one of the interrupt conditions occurs in the registers. this pin should be pull-up externally. 17 nc ? no connect 18 nc ? no connect 19 eecs opu eeprom chip select this signal is used to select an external eeprom device 20 nc ? no connect 21 nc ? no connect 22 p2led3 opd port 2 led indicator see the description in pins 6, 7, and 8. 23 dgnd gnd digital io ground 24 vddco p 1.2v core voltage output. (internal 1.2v ldo power supply output) this pin is used to provide 1.2v power supply to all 1.2v power vddc, vdda and vddap. it is recommended the pin should be connected to 3.3v power rail by a 100ohm resistor for the internal ldo application. 25 nc ? no connect 26 eeen ipd eeprom enable eeprom is enabled and connected when this pin is pull-up. eeprom is disabled when this pin is pull-down or no connect. 27 p1led3 opd port 1 led indicator see the description in pins 3, 4, and 5. 28 eedo opd eeprom data out this pin is connected to di input of the serial eeprom. 29 eesk opd eeprom serial clock 4 s serial clock to load configuration data from the serial eeprom. 30 eedi ipd eeprom data in this pin is connected to do output of the serial eeprom. 31 nc ? no connect 32 vddio p 3.3v digital i/o v dd . 33 vddio p 3.3v digital i/o v dd . 34 dgnd gnd digital ground 35 dgnd gnd digital ground 36 pwrdn ipu full-chip power-down input. active low. 37 agnd gnd analog ground 38 vdda p 1.2v analog v dd 39 agnd gnd analog ground 40 nc ? no connect
micrel, inc. ksz8842-pmql/pmbl october 2007 13 m9999-100207-1. 5 pin number pin name type pin function 41 nc ? no connect 42 agnd gnd analog ground 43 vdda p 1.2v analog v dd 44 nc ? no connect 45 rxp1 i/o physical receive (mdi) or transmit (mdix)signal (+ differential) 46 rxm1 i/o physical receive (mdi) or transmit (mdix) signal (? differential) 47 agnd gnd analog ground 48 txp1 i/o physical transmit (mdi) or receive (mdix) signal (+ differential) 49 txm1 i/o physical transmit (mdi) or receive (mdix) signal (? differential) 50 vddatx p 3.3v analog v dd 51 vddarx p 3.3v analog v dd 52 rxm2 i/o port 2 physical receive (mdi ) or transmit (mdix)signal (- differential) 53 rxp2 i/o port 2 physical receive(mdi) or transmit (mdix) signal (+ differential) 54 agnd gnd analog ground 55 txm2 i/o port 2 physical transmit (mdi) or receive (mdix) signal (- differential) 56 txp2 i/o port 2 physical transmit (mdi) or receive (mdix) signal (+ differential) 57 vdda p 1.2 analog v dd 58 agnd gnd analog ground 59 nc ? no connect 60 nc ? no connect 61 iset o set physical transmit output current pull-down this pin with a 3.01k 1% resistor to ground. 62 agnd gnd analog ground 63 vddap p 1.2v analog v dd for pll 64 agnd gnd analog ground 65 x1 i 66 x2 o 25mhz crystal/oscillato r clock connections pins (x1, x2) connect to a crystal. if an os cillator is used, x1 connects to a 3.3v tolerant oscillator and x2 is not connected. note: clock is 50ppm for both crystal and oscillator. 67 rstn ipu hardware reset, active low rstn will cause the ksz8842-pmql to reset all of its functional blocks. rstn must be asserted for a minimum duration of 10 ms. 68 par i/o pci parity even parity computed for pad [31:0] and cbe [3:0]n, master drives par for address and write data phase, target drives par for read data phase. 69 framen i/o pci cycle frame this signal is asserted low to indicate t he beginning of the address phase of the bus transaction and de-asserted before the fi nal transfer of the data phase of the transaction in a bus master mode. as a targ et, the device monitors this signal before decoding the address to check if the cu rrent transaction is addressed to it. 70 irdyn i/o pci initiator ready as a bus master, this signal is asserted low to indicate valid data phases on pad [31:0] during write data phases, indicates it is read y to accept data during read data phases. as a target, it?ll monitor this irdyn signal that indicates the master has put the data on the bus.
micrel, inc. ksz8842-pmql/pmbl october 2007 14 m9999-100207-1. 5 pin number pin name type pin function 71 trdyn i/o pci target ready as a bus target, this signal is asserted low to indicate valid data phases on pad [31:0] during read data phases, indicating it is ready to accept data during write data phases. as a master, it will monitor this trdyn sign al that indicates the target is ready for data during read/write operation. 72 stopn i/o pci stop this signal is asserted low by the target device to stop the current transaction. 73 idsel i/o pci initialization device select this signal is used to select the ksz8842- pmql during configuration read and write transactions. 74 devseln i/o pci device select this signal is asserted low when it is selecte d as a target during a bus transaction. as a bus master, the ksz8842-pmql samples this signal to insure that the destination address for the data transfer is recognized by a pci target. 75 reqn o pci bus request the ksz8842-pmql will assert this signal low to request pci bus master operation. 76 gntn i pci bus grant this signal is asserted low to indicate to the ksz8842-pmql that it has been granted the pci bus master operation. 77 perrn i/o pci parity error the ksz8842-pmql as a master or target will assert this signal low to indicate a parity error on any incoming data. as a bus master, it will monitor this signal on all write operations. 78 dgnd gnd digital i/o ground 79 vddio p 3.3v digital i/o v dd 80 serrn o pci system error this system error signal is asserted low by the ksz8842-pmql.this signal is used to report address parity errors. 81 nc ? no connect 82 nc ? no connect 83 nc ? no connect 84 nc ? no connect 85 cbe3n i 86 cbe2n i 87 cbe1n i 88 cbe0n i command and byte enable these signals are multiplexed on the same pci pins. during the address phase, these lines define the bus command. during the data phase, these lines are used as byte enables. the byte enables are valid for the entire data phase and determine which byte lanes carry meaningful data. 89 pad31 i/o pci address / data 31 address and data are multiplexed on the al l of the pad pins. the pad pins carry the physical address during the first clock cyc le of a transaction, and carry data during the subsequent clock cycles. 90 dgnd gnd digital core ground 91 vddc p 1.2v digital core v dd 92 vddio p 3.3v digital i/o v dd 93 pad30 i/o pci address / data 30 94 pad29 i/o pci address / data 29 95 pad28 i/o pci address / data 28
micrel, inc. ksz8842-pmql/pmbl october 2007 15 m9999-100207-1. 5 pin number pin name type pin function 96 pad27 i/o pci address / data 27 97 pad26 i/o pci address / data 26 98 pad25 i/o pci address / data 25 99 pad24 i/o pci address / data 24 100 pad23 i/o pci address / data 23 101 pad22 i/o pci address / data 22 102 pad21 i/o pci address / data 21 103 pad20 i/o pci address / data 20 104 pad19 i/o pci address / data 19 105 pad18 i/o pci address / data 18 106 pad17 i/o pci address / data 17 107 dgnd gnd digital i/o ground 108 vddio p 3.3v digital i/o v dd 109 pad16 i/o pci address / data 16 110 pad15 i/o pci address / data 15 111 pad14 i/o pci address / data 14 112 pad13 i/o pci address / data 13 113 pad12 i/o pci address / data 12 114 pad11 i/o pci address / data 11 115 pad10 i/o pci address / data 10 116 pad9 i/o pci address / data 9 117 pad8 i/o pci address / data 8 118 pad7 i/o pci address / data 7 119 pad6 i/o pci address / data 6 120 pad5 i/o pci address / data 5 121 pad4 i/o pci address / data 4 122 pad3 i/o pci address / data 3 123 dgnd gnd digital i/o ground 124 dgnd gnd digital core ground 125 vddio p 3.3v digital i/o v dd 126 pad2 i/o pci address / data 2 127 pad1 i/o pci address / data 1 128 pad0 i/o pci address / data 0 table 1. ksz8842-pmql pin description notes: p = power supply. gnd = ground. i = input. o = output. i/o = bi-directional. ipd = input with internal pull-down. ipu = input with internal pull-up. opd = output with internal pull-down. opu = output with internal pull-up.
micrel, inc. ksz8842-pmql/pmbl october 2007 16 m9999-100207-1. 5 balls description of KSZ8842-PMBL ball number ball name type ball function a8 test_en i test enable. for normal operation, pull-down this pin to ground. c7 scan_en i scan test scan mux enable. for normal operation, pull-down this pin to ground. b7 p1led2 opu a7 p1led1 opu c6 p1led0 opu b6 p2led2 opu a6 p2led1 opu b5 p2led0 opu port 1 and port 2 led indicators 1 defined as follows: switch global control register 5: sgcr5 bit [15,9] [0,0] default [0,1] p1led3 2 /p2led3 ? ? p1led2/p2led2 link/act 100link/act p1led1/p2led1 full duplex/col 10link/act p1led0/p2led0 speed full duplex reg. sgcr5 bit [15,9] [1,0] [1,1] p1led3 2 p2led3 act ? p1led2/p2led2 link ? p1led1/p2led1 full duplex/col ? p1led0/p2led0 speed ? notes: 1. link = on; activity = blink; link/act = on/blink; full dup/col = on/blink; full duplex = on (full duplex); off (half duplex) speed = on (100base-t); off (10base-t) 2. p1led3 is ball b3. p2led3 is ball c3. port 1 and port 2 led indicators 3 for repeater mode defined as follows: switch global control regis ter 5: sgcr5 bit [15,9] [0,0] default [0,1] [1,0] [1,1] p1led3 , p2led3 rpt_col, rpt_act ? p1led2, p2led2 rpt_link3/rx, rpt_err3 ? p1led1, p2led1 rpt_link2/rx, rpt_err2 ? p1led0, p2led0 rpt_link1/rx, rpt_err1 ? note 3: rpt_col = blink; rpt_link3/rx (host port) = on/blink; rpt_link2/rx (port 2) = on/blink; rpt_link1/rx (port 1) = on/blink; rpt_act = on if any activity; rpt_err3 (host port) = on if any crc error; rpt_err2 (port 2) = on if any crc error; rpt_err1 (port 1) = on if any crc error; a5 pclk ipd pci bus clock. this clock provides the timing for all pci bus phases. the rising edge
micrel, inc. ksz8842-pmql/pmbl october 2007 17 m9999-100207-1. 5 ball number ball name type ball function defines the start of each phase. the clock maximum frequency is 33mhz. b4 intrn opd interrupt request. active low signal to ho st cpu to request an interrupt when any one of the interrupt conditions occurs in the registe rs. this pin should be pull-up externally. a4 eecs opu eeprom chip select. this signal is used to select an external eeprom device c3 p2led3 opd port 2 led indicator see the description in ball b5, b6 and a6. a3 eeen ipd eeprom enable eeprom is enabled and connect ed when this pin is pull-up. eeprom is disabled when this pin is pull-down or no connect. b3 p1led3 opd port 1 led indicator see the description in ball c7, a7 and b7. b2 eedo opd eeprom data out: this pin is connected to di input of the serial eeprom. a2 eesk opd eeprom serial clock: a 4 s serial output clock to load confi guration data from the serial eeprom. a1 eedi ipd eeprom data in: this pin is connected to do output of the serial eeprom. b1 pwrdn ipu full-chip power-down. active low. c1 rxp1 i/o port 1 physical receive (mdi) or transmit (mdix) signal (+ differential) c2 rxm1 i/o port 1 physical receive (mdi) or transmit (mdix) signal (? differential) d1 txp1 i/o port 1 physical transmit (mdi) or receive (mdix) signal (+ differential) d2 txm1 i/o port 1 physical transmit (mdi) or receive (mdix) signal (? differential) f2 rxm2 i/o port 2 physical receive (mdi ) or transmit (mdix)signal (- differential) f1 rxp2 i/o port 2 physical receive(mdi) or transmit (mdix) signal (+ differential) g2 txm2 i/o port 2 physical transmit (mdi) or receive (mdix) signal (- differential) g1 txp2 i/o port 2 physical transmit (mdi) or receive (mdix) signal (+ differential) g3 iset o set physical transmit output current. pull-down this ball with a 3.01k 1% resistor. h1 x1 i h2 x2 o 25mhz crystal/oscillator clock connections balls (x1, x2) connect to a crystal. if an oscillat or is used, x1 connects to a 3.3v tolerant oscillator and x2 is a no connect. note: clock is 50ppm for both crystal and oscillator. j1 rstn ipu hardware reset, active low rstn will cause the KSZ8842-PMBL to reset all of its functional blocks. rstn must be asserted for a minimum duration of 10 ms. j2 par o pci parity even parity computed for pad [31:0] and cbe[3: 0]n, master drives par for address and write data phase, target driv es par for read data phase. k1 framen i/o pci cycle frame this signal is asserted low to indicate t he beginning of the address phase of the bus transaction and de-asserted before the final trans fer of the data phase of the transaction in a bus master mode. as a target, the device moni tors this signal before decoding the address to check if the current transaction is addressed to it.
micrel, inc. ksz8842-pmql/pmbl october 2007 18 m9999-100207-1. 5 ball number ball name type ball function k2 irdyn i/o pci initiator ready as a bus master, this signal is asserted low to indicate valid data phases on pad [31:0] during write data phases, indicates it is ready to accept data during read data phases. as a target, it?ll monitor this irdyn signal that in dicates the master has put the data on the bus. h3 trdyn i/o pci target ready as a bus target, this signal is asserted low to indicate valid data phases on pad [31:0] during read data phases, indicating it is ready to acc ept data during write data phases. as a master, it will monitor this trdyn signal that indicates the target is ready for data during read/write operation. j3 stopn i/o pci stop this signal is asserted low by the tar get device to stop the current transaction k3 idsel i/o pci initial ization device select. this signal is used to select the ksz8842-pmql /pmbl during configuration read and write transactions. h4 devseln i/o pci device select this signal is asserted low when it is selected as a target during a bus transaction. as a bus master, the KSZ8842-PMBL samples this signal to insure that the destination address for the data transfer is recognized by a pci target. j4 reqn o pci request the KSZ8842-PMBL will assert this signal low to request pci bus master operation. k4 gntn i pci grant this signal is asserted low to indicate to t he KSZ8842-PMBL that it has been granted the pci bus master operation. h5 perrn i/o pci parity error the KSZ8842-PMBL as a master or target will as sert this signal low to indicate a parity error on any incoming data. as a bus master, it wi ll monitor this signal on all write operations. j5 serrn o pci system error this system error signal is asserted low by the KSZ8842-PMBL.this signal is used to report address parity errors. k5 cbe3n i k6 cbe2n i j6 cbe1n i h6 cbe0n i command and byte enable these signals are multiplexed on the same pc i pins. during the address phase, these lines define the bus command. during t he data phase, these lines are used as byte enables. the byte enables are valid for the entire data phase and determine which byte lanes carry meaningful data. k7 pad31 i/o pci address / data 31 address and data are multiplexed on the al l of the pad balls. the pad pins carry the physical address during the first clock cyc le of a transaction, and carry data during the subsequent clock cycles. j7 pad30 i/o pci address / data 30 h7 pad29 i/o pci address / data 29 k8 pad28 i/o pci address / data 28 j8 pad27 i/o pci address / data 27 h8 pad26 i/o pci address / data 26 k9 pad25 i/o pci address / data 25 j9 pad24 i/o pci address / data 24 k10 pad23 i/o pci address / data 23
micrel, inc. ksz8842-pmql/pmbl october 2007 19 m9999-100207-1. 5 ball number ball name type ball function j10 pad22 i/o pci address / data 22 h9 pad21 i/o pci address / data 21 h10 pad20 i/o pci address / data 20 g8 pad19 i/o pci address / data 19 g9 pad18 i/o pci address / data 18 g10 pad17 i/o pci address / data 17 f8 pad16 i/o pci address / data 16 f9 pad15 i/o pci address / data 15 f10 pad14 i/o pci address / data 14 e8 pad13 i/o pci address / data 13 e9 pad12 i/o pci address / data 12 e10 pad11 i/o pci address / data 11 d10 pad10 i/o pci address / data 10 d9 pad9 i/o pci address / data 9 d8 pad8 i/o pci address / data 8 c10 pad7 i/o pci address / data 7 c9 pad6 i/o pci address / data 6 c8 pad5 i/o pci address / data 5 b10 pad4 i/o pci address / data 4 b9 pad3 i/o pci address / data 3 b8 pad2 i/o pci address / data 2 a10 pad1 i/o pci address / data 1 a9 pad0 i/o pci address / data 0 c5 vddc p 1.2v digital core v dd c4 vddco p 1.2v core voltage output. (internal 1.2v ldo power supply output) this ball is used to provide 1.2v power supply to all 1.2v power vddc and vdda. it is recommended the ball should be connected to 3.3v power rail by a 100ohm resistor for the internal ldo application. d3, e3, f3 vdda p 1.2v analog v dd d7, e7, f7, g4, g5, g6, g7 vddio p 3.3v digital i/o v dd e1 vddatx p 3.3v analog v dd e2 vddarx p 3.3v analog v dd d4, d5, d6, e4, e5, e6, f4, f5, f6 gnd gnd ground table 2. KSZ8842-PMBL ball description
micrel, inc. ksz8842-pmql/pmbl october 2007 20 m9999-100207-1. 5 functional description the ksz8842-pmql/pmbl contains one pci interface unit, two 10/100 physical layer transceivers (phys), three mac units, and a rx/tx dma channel all integrated with a layer-2 switch. physical signal transmission and reception are enhanced through the use of analog circuits in the phy that make the design more efficient and allow for low power consumption. functional overview: pci bus interface unit pci bus interface the pci bus interface implements pci v2.2 bus protocols and configuration space. the ksz8842-pmql/pmbl supports bus master reads and writes to cpu memory, an d cpu access to on-chip r egister space. when the cpu reads and writes the configuration registers of the ksz8842-pmql/pmbl, it is as a slave. so the ksz8842- pmql/pmbl can be either a pci bus master or slave. the pci bus interface is also responsible for managing the dma interfaces and the host processors acce ss. arbitration logic within the pci bus interface unit accept s bus requests from the txdma logic and rxdma logic. the pci bus interface also manages interrupt generation for a host processor. txdma logic and tx buffer manager the ksz8842-pmql/pmbl supports a multi-frame, multi- fragment dma gather process. descriptors representing frames are built and linked in system me mory by a host processor. the txdma l ogic is responsible for transferring the multi-fragment frame data from the host memory into the tx buffer. the ksz8842-pmql/pmbl uses 4k bytes of transmit data buffer between the txdma logic and transmit mac. when the txdma logic determines there is enough space availabl e in the tx buffer, the tx dma logic will move any pending frame data into the tx buffer. the management me chanism depends on the transmit descriptor list. rxdma logic and rx buffer manager the ksz8842-pmql/pmbl supports a multi-frame, multi-fr agment dma scatter process. descriptors representing frames are built and linked in system me mory by the host processo r. the rxdma logic is responsible for transferring the frame data from the rx buffer to the host memory. the ksz8842-pmql/pmbl uses 4k bytes of receive data buffer between the receive mac and rxdma logic. the management mechanism depends on the receive descriptor list. functional overview: physi cal layer transceiver (phy) 100base-tx transmit the 100base-tx transmit function performs parallel to serial conversion, 4b/5b codi ng, scrambling, nrz-to-nrzi conversion, and mlt3 encoding and transmission. the circuitry starts with a parallel-to-s erial conversion, which converts the mii data from the mac into a 125mhz serial bit stream. the data and control stream is then converted in to 4b/5b coding, followed by a scrambler. the serialized data is further converted from nrz-to-nrzi format, and then transmitted in mlt3 current output. the output current is set by an external1% 3.01k ? resistor for the 1:1 transformer ratio. the output signal has a typical rise/fall time of 4ns and comp lies with the ansi tp-pmd standard regarding amplitude balance, overshoot, and timing jitter. the wave-shaped 10base-t output is al so incorporated into the 100base-tx transmitter. 100base-tx receive the 100base-tx receiver function perf orms adaptive equalization, dc restoration, mlt3-t o-nrzi conversion, data and clock recovery, nrzi-to-nrz conver sion, de-scrambling, 4b/5b decoding, a nd serial to parallel conversion. the receiving side starts with the equalization filter to co mpensate for inter-symbol interf erence (isi) over the twisted pair cable. since the amplitude loss and phase distortion is a function of the cable length, the equalizer must adjust its characteristics to optimize performance. in this design, the variable equalizer makes an initial estimation based on comparisons of incoming signal strength against some know n cable characteristics, and then tunes itself for
micrel, inc. ksz8842-pmql/pmbl october 2007 21 m9999-100207-1. 5 optimization. this is an ongoing process and self-adjusts against environmental changes such as temperature variations. next, the equalized signal goes through a dc restoration and dat a conversion block. the dc restoration circuit is used to compensate for the effect of baseline wander and to improve the dynamic range. the differential data conversion circuit converts the mlt3 format back to nrzi. the slicing threshold is also adaptive. the clock recovery circuit extracts the 125mhz clock from th e edges of the nrzi signal. this recovered clock is then used to convert the nrzi signal into the nrz format. this signal is sent through the de- scrambler followed by the 4b/5b decoder. finally, the nrz serial data is converted to the mii format and prov ided as the input data to the mac. pll clock synthesizer (recovery) the internal pll clock synthesizer generates 125mhz, 62 .5mhz, 41.66mhz, and 25mhz clocks by setting the on-chip bus speed control register obcr for ks z8842-pmql/pmbl system timing. thes e internal clocks are generated from an external 25mhz crystal or oscillator. note: default setting is 25mhz in obcr register, recommend s the software driver to set it to 125mhz for best performance. scrambler/de-scrambler (100base-tx only) the purpose of the scrambler is to spread the power spectr um of the signal to reduce electromagnetic interference (emi) and baseline wander. transmitted data is scrambled through the use of an 11-bit wide linear feedback shift register (lfsr). the scrambler generates a 2047-bit non-r epetitive sequence, and the rece iver then de-scrambles the incoming data stream using the same sequence as at the transmitter. 10base-t transmit the 10base-t driver is incorporated wi th the 100base-tx driver to allow fo r transmission using the same magnetic. they are internally wave-shaped and pre-emphasized into out puts with typical 2.3v amplitude. the harmonic contents are at least 27db below the fundamental frequency when driven by an all-ones manchester-encoded signal. 10base-t receive on the receive side, input buffers and level detecting squelch ci rcuits are employed. a differential input receiver circuit and a phase-locked loop (pll) perform the decoding functi on. the manchester-encoded data stream is separated into clock signal and nrz data. a squelch circuit rejects signals wi th levels less than 400mv or with short pulse widths to prevent noise at the rxp-or-rxm input from falsely tri ggering the decoder. when the input exceeds the squelch limit, the pll locks onto the incoming signal and the ksz8842-pmq l/pmbl decodes a data frame. the receiver clock is maintained active during idle periods in between data reception. power management the ksz8842-pmql/pmbl features a per port power-down mo de. to save power, the user can power-down a port that is not in use by setting bit 11 in either p1cr4 or p1 mbcr register for port 1, and set bit 11 in either p2cr4 or p2mbcr register for port 2. to bring the por t back up, reset bit 11 in these registers. in addition, there is a full switch power-down mode by pwrd n pin/ball 36. when this pin/ball is pulled-down, the entire chip powers down. transitioning this pin/ball from pull-down to pull-up results in a power up and chip reset. mdi/mdi-x auto crossover to eliminate the need for crossover cables between si milar devices, the ksz8842-pmql/pmbl supports hp-auto mdi/mdi-x and ieee 802.3u st andard mdi/mdi-x auto crossover. hp-auto mdi/mdi-x is the default. the auto-sense function detects remote transmit and receive pairs and correctly assigns the transmit and receive pairs for the ksz8842-pmql/pmbl device. this feature is extremel y useful when end users are unaware of cable types in addition to saving on an additional uplink configuration connec tion. the auto-crossover feature can be disabled through the port control registers.
micrel, inc. ksz8842-pmql/pmbl october 2007 22 m9999-100207-1. 5 the ieee 802.3u standard mdi and mdi-x definitions are: mdi mdi-x rj45 pins signals rj45 pins signals 1 td+ 1 rd+ 2 td- 2 rd- 3 rd+ 3 td+ 6 rd- 6 td- table 3. mdi/mdi-x pin definitions straight cable a straight cable connects an mdi device to an mdi-x devic e or an mdi-x device to an mdi device. the following diagram shows a typical straight cable connection between a network interface card (nic) (mdi) and a switch, or hub (mdi-x). figure 4. typical straight cable connection
micrel, inc. ksz8842-pmql/pmbl october 2007 23 m9999-100207-1. 5 crossover cable a crossover cable connects an mdi device to another mdi dev ice, or an mdi-x device to another mdi-x device. the following diagram shows a typical crossover cable connec tion between two switches or hubs (two mdi-x devices). figure 5. typical crossover cable connection auto negotiation the ksz8842-pmql/pmbl conforms to the auto negotiation pr otocol as described by the 802.3 committee to allow the channel to operate at 10base-t or 100base-tx. auto negotiation allows unshielded twisted pair (utp) link pa rtners to select the best common mode of operation. in auto negotiation, the link part ners advertise capabilities ac ross the link to ea ch other. if auto negotiation is not supported or the link partner to the ksz8842-pmql/pmbl is forced to bypass auto negotiation, the mode is set by observing the signal at the receiver. this is known as parallel mode because while the transmitter is sending auto negotiation advertisements, the receiver is listeni ng for advertisements or a fixed signal protocol. the link setup is shown in the following flow diagram (figure 6).
micrel, inc. ksz8842-pmql/pmbl october 2007 24 m9999-100207-1. 5 start auto negotiation force link setting listen for 10base-t link pulses listen for 100base-tx idles ttempt auto negotiation link mode set bypass auto negotiation and set link mode link mode set ? parallel operation join flow no yes no yes figure 6. auto negotiation and parallel operation linkmd cable diagnostics the ksz8842-pmql/pmbl linkmd uses time domain reflectometry (tdr) to analyze the cabling plant for common cabling problems such as open circuits, s hort circuits, and impedance mismatches. linkmd works by sending a pulse of known amplitude and duration down the mdi and mdi-x pairs and then analyzes the shape of the reflected signal. timing t he pulse duration gives an indication of the distance to the cabling fault with a maximum distance of 200m and an accuracy of 2m. internal circuitry displays the tdr information in a user-readable digital format. access linkmd is initiated by accessing regist er p1vct/p2vct, the linkmd control/st atus register, in conjunction with register p1cr4/p2cr4, the 100 base-tx phy controller register.
micrel, inc. ksz8842-pmql/pmbl october 2007 25 m9999-100207-1. 5 usage linkmd can be used at any time by making sure auto mdix has been disabled. to disable auto-mdix, write a ?1? to p1cr4[10] for port 1 or p2cr4[10] for po rt 2 to enable manual control over the pai r used to transmit the linkmd pulse. the self-clearing cable diagnostic test e nable bit, p1vct[15] for port 1 or p2vct[15] for port 2, is set to ?1? to start the test on this pair. when bit p1vct[15] or p2vct[15] returns to ?0?, the test is complete. the test result is returned in bit p1vct[14-13] or p2vct[14-13] and the distance is returned in bits p1vct[8-0] or p2vct[8-0]. the cable dia gnostic test results are as follows: 00 = valid test, normal condition 01 = valid test, open circuit in cable 10 = valid test, short circuit in cable 11 = invalid test, linkmd failed iif p1vct[14-13]=11 or p2vct[14 -13]=11, this indicates an invalid test, and occurs when the ksz8842-pmql/pmbl is unable to shut down the link partner. in this instance, the test is not run, as it is not possible for the ksz8842- pmql/pmbl to determine if the detected signal is a reflection of the signal generated or a signal from another source. cable distance (in meters) can be app roximated by the following formula: distance = p1vct[8-0] x 0.4m distance = p1vct[8-0] x 0.4m this constant may be calibrated for different cabling conditi ons, including cables with a velocity of propagation that varies significantly from the norm. functional overview : mac and switch address lookup the internal lookup table stores mac addresses and their associat ed information. it contains a 1k unicast address table plus switching information. the ksz8842-pmql/pmbl is guaranteed to learn 1k addresse s and distinguishes itself from hash-based lookup tables, which depending on the operat ing environment and probab ilities, may not guarant ee the absolute number of addresses it can learn. learning the internal lookup engine updates its table with a new entry if the following conditions are met: 1. the received packet's source address ( sa) does not exist in the lookup table. 2. the received packet is good; the packet has no receiving errors, and is of legal length. the lookup engine inserts the qualified sa in to the table, along with the port num ber and time stamp. if the table is full, the last entry of the t able is deleted to make room for the new entry. migration the internal lookup engine also monito rs whether a station has moved. if a st ation has moved, it updates the table accordingly. migration happens when the following conditions are met: 1. the received packet's sa is in the table but t he associated source port information is different. 2. the received packet is good; the packet has no receiving errors, and is of legal length. the lookup engine updates the existing record in t he table with the new source port information. aging the lookup engine updates the time stamp information of a record whenever the corresponding sa appears. the time stamp is used in the aging process. if a record is not updated for a period of time, the lookup engine removes the record from the table. the lookup engine constantly per forms the aging process and continuously removes aging records. the aging period is about 200 seconds. this featur e can be enabled or disabled through global register sgcr1[10]).
micrel, inc. ksz8842-pmql/pmbl october 2007 26 m9999-100207-1. 5 forwarding the ksz8842-pmql/pmbl forwards packets using the algorith m that is depicted in the following flowcharts. figure 7 shows stage one of the forwarding algorithm where the search engine looks up the vlan id, static table, and dynamic table for the destination address, and comes up with ?port to forward 1? (ptf1). ptf1 is then further modified by spanning tree, igmp snooping, port mirroring, and port vlan processes to come up with ?port to forward 2? (ptf2), as shown in figure 8. the packet is sent to ptf2. start vlan id valid? ptf1 = null search static table search complete. get ptf1 from static mac table dynamic table search search complete. get ptf1 from vlan table search complete. get ptf1 from dynamic mac table ptf1 - search vlan table - ingress vlan filtering - discard npvid check yes no found not found found not found this search is based on da or da+fid this search is based on da+fid figure 7. destination address lookup flow chart, stage 1
micrel, inc. ksz8842-pmql/pmbl october 2007 27 m9999-100207-1. 5 spanning tree process ptf1 igmp process port mirror process port vlan membership check ptf2 - check receiving port's receive enable bit - check destination port's transmit enable bit - check whether packets are special (bpdu) or s p ecified - rx mirror - tx mirror - rx or tx mirror - rx and tx mirror - applied to mac #1 and mac #2 - igmp will be forwarded to the host port figure 8. destination address resolution flow chart, stage 2 the ksz8842-pmql/pmbl will not forward the following packets: 1. error packets. these include framing errors, frame check sequence (f cs) errors, alignment errors, and illegal size packet errors. 2. 802.3x pause frames. the ksz8842-pmql/pmbl intercepts these packets and performs flow control. 3. "local" packets. based on destination address (da) lookup. if the destinat ion port from the lookup table matches the port from which the packet originated, the packet is defined as "local." switching engine the ksz8842-pmql/pmbl features a high-p erformance switching engine to move data to and from the mac?s packet buffers. it operates in store and forward mode, while the e fficient switching mechanism reduces overall latency. the switching engine has a 32kb internal frame buffer. this re source is shared between all the ports. there are a total of 256 buffers available. each buffer is sized at 128b.
micrel, inc. ksz8842-pmql/pmbl october 2007 28 m9999-100207-1. 5 mac operation the ksz8842-pmql/pmbl strictly abides by ieee 802.3 standards to maximize co mpatibility. additionally, there is an added mac filtering function to filter unicast packets. the mac f iltering function is useful in applications such as voip where restricting certain pa ckets reduces congestion and th us improves performance. inter packet gap (ipg) if a frame is successfully transmitted, the minimum 96-bits time for ipg is measured between two consecutive packets. if the current packet is experiencing colli sions, the minimum 96-bits time for ipg is measured from carrier sense (csr) to the next transmit packet. back-off algorithm the ksz8842-pmql/pmbl implements the ieee standard 802.3 binary exponential back-off algorithm in half-duplex mode, and optional "aggressive mode" back- off. after 16 collisions, the packet is optionally dropped depending on the switch configuration in sgcr1[8]. late collision if a transmit packet experienc es collisions after 512 bit times of t he transmission, the packet is dropped. illegal packet size the ksz8842-pmql/pmbl discards packets that are less than 64 bytes in size and can be programmed to accept packet sizes up to 1536 bytes in sgcr2[1]. the ksz8842-pmql/pmbl can also be programmed for special applications to accept packet si zes up to 1916 bytes in sgcr2[2]. flow control the ksz8842-pmql/pmbl supports standard 802.3x flow control frames on both transmit and receive sides. on the receive side, if the ksz8842-p mql/pmbl receives a pause control frame, the ksz8842-pmql/pmbl will not transmit the next normal frame until the time r, specified in the pause control fram e, expires. if another pause frame is received before the current timer expires, the timer will be updated with the new value in the second pause frame. during this period (while it is flow controlled), only flow control packets from the ksz 8842-pmql/pmbl are transmitted. on the transmit side, the ksz8842-pmql/pmbl has intelligent and efficient ways to determine when to invoke flow control. the flow control is based on availability of the syst em resources, including avail able buffers, available transmit queues, and available receive queues. the ksz8842-pmql/pmbl will flow control a port that has just received a packet if the destination port resource is busy. the ksz8842-pmql/pmbl issues a flow control fram e (xon), containing the maximum pause time defined in ieee standard 802.3x. once the resour ce is freed up, the ksz 8842-pmql/pmbl sends out the other flow control frame (xoff) with zero pause time to tu rn off the flow control (turn on transmissi on to the port). a hysteresis feature is provided to prevent the flow control mechanism from being constantly activated and deactivated. half-duplex backpressure a half-duplex backpressur e option (not in ieee 802.3 st andards) is also pr ovided. the activati on and deactivation conditions are the same in full-duplex mode. if backpress ure is required, the ksz8842-p mql/pmbl sends preambles to defer the other stations' transmi ssion (carrier sense deference). to avoid jabber and excessive deference (as defined in the 802.3 standard), after a certain time, the ksz8842- pmql/pmbl discontinues the carrier sense and then raises it again quickly. this short silent time (no carrier sense) prevents other stations from se nding out packets thus keepi ng other stations in a carrie r sense deferred state. if the port has packets to send during a backpressure situation, the carrier sense type backpre ssure is interrupted and those packets are transmitted instead. if there are no additional packets to send, carrier sense type backpressure is reactivated again until switch resource s free up. if a collision occurs, the binary exponential back-off algorithm is skipped and carrier sense is generated immediately, thus reduci ng the chance of further collisions and carrier sense is maintained to prevent packet reception. to ensure no packet loss in 10 base-t or 100 base-tx hal f-duplex modes, the user mu st enable the following: 1. aggressive back off (bit 8 in sgcr1) 2. no excessive collision drop (bit 3 in sgcr2) note: these bits are not set by defaul t, since this is not the ieee standard.
micrel, inc. ksz8842-pmql/pmbl october 2007 29 m9999-100207-1. 5 broadcast storm protection the ksz8842-pmql/pmbl has an intelligent option to protec t the switch system from re ceiving too many broadcast packets. as the broadcast packets are forwarded to all port s except the source port, an excessive number of switch resources (bandwidth and available space in transmit queues) may be utilized. the ksz8842-pmql/pmbl has the option to include ?multicast packets? for storm control. t he broadcast storm rate parameters are programmed globally, and can be enabled or disabled on a per port basis in p1cr 1[7] and p2cr1[7]. the rate is based on a 67ms interval for 100base-t and a 670ms interval for 10bas e-t. at the beginning of each interval, the counter is cleared to zero and the rate limit mechanism starts to count the number of byte s during the interval. the rate definition is described in sgcr3[15:18]. the default setting is 0x63 (99 decimal). this is equal to a rate of 1% minimum size packets, calculated as follows: 148,800 frames/sec x 67 ms/interval x 1% = 99 frames/interval (approx.) = 0x63 where 148,800 frames/sec is based on 64-byte blocks of 100base-t packets with 12 bytes of ipg and 8 bytes of preamble between packets. repeater mode when ksz8842-pmql/pmbl is set to repeater mode (sgcr3[7 ] = 1), it only works on 100bt half-duplex mode. in repeater enabled mode, all i ngress packets will broadcast to other two ports wi thout mac check and learning. before setting the device to repeater mode, the user has to set bit 13 (100mbps), bit 12 (auto-negotiation disabled) and bit 8 (half duplex) in both p1mbcr and p2mbcr registers as well as to set bit 6 (host half duplex) in sgcr3 register for repeater mode. the latency in repeater mode is defined from the 1st bit of da into the ingress port 1 to the 1st bit of da out of the egress port 2. the minimum is 270 ns and the maximum is 310 ns (one clock skew of 25 mhz between tx and rx). clock generator the x1 and x2 pin/balls are connected to a 25mhz crystal. x1 can also serve as the connector to a 3.3v, 25mhz oscillator (as described in the pin/ball description). the pci bus interface s upports a maximum speed of 33mhz pclk (pci bus clock). advanced switch functions spanning tree support to support spanning tree, the host port is the designated port for the processor. the other ports can be configured in one of the five spanni ng tree states via ?transmit enable?, ?receive enable? and ?learning disable? register settings in registers p1cr2 and p2cr2 for ports 1 and 2, respectively. table 4 shows the port setting and software actions taken for each of the five spanning tree states. disable state port setting software action the port should not forward or receive any packets. learning is disabled. ?transmit enable = 0, receive enable = 0, learning disable = 1? the processor should not send any packets to the port. the switch may still send specific packets to the processor (packets that match some entries in the ?static mac table? with ?overriding bit? set) and the processor should discard those packets. address learning is disabled on the port in this state. blocking state port setting software action only packets to the processor are forwarded. ?transmit enable = 0, receive enable = 0, learning disable = 1? the processor should not send any packets to the port(s) in this state. the processor should program the ?static mac table? with the entries that it needs to rece ive (for example, bpdu packets). the ?overriding? bit should also be set so that the switch will forward those specific packets to the processor. address learning is disabled on the port in this state. listening state port setting software action only packets to and from the processor are ?transmit enable = 0, receive enable = 0, learning disable = 1? the processor should program the ?static mac table? with the entries that it needs to receive (for example, bpdu packets). the ?overriding? bit should be set so that the switch will forward those
micrel, inc. ksz8842-pmql/pmbl october 2007 30 m9999-100207-1. 5 forwarded. learning is disabled. specific packets to the processor. the processor may send packets to the port(s) in this stat e. address learning is disabled on the port in this state. learning state port setting software action only packets to and from the processor are forwarded. learning is enabled. ?transmit enable = 0, receive enable = 0, learning disable = 0? the processor should program the ?static mac table? with the entries that it needs to receive (for example, bpdu packets). the ?overriding? bit should be set so that the switch will forward those specific packets to the processor. the processor may send packets to the port(s) in this stat e. address learning is enabled on the port in this state. forwarding state port setting software action packets are forwarded and received normally. learning is enabled. ?transmit enable = 1, receive enable = 1, learning disable = 0? the processor programs the ?static mac table? with the entries that it needs to receive (for example, bpdu packets). the ?overriding? bit is set so that t he switch forwards those specific packets to the processor. the processor can send packets to the port(s) in this state. address lear ning is enabled on the port in this state. table 4. ksz8841-pmql/pmbl eeprom format igmp support for internet group management protocol (igmp) suppo rt in layer 2, the ksz8842-pmql/pmbl provides two components: ?igmp? snooping the ksz8842-pmql/pmbl traps igmp pa ckets and forwards them only to the processor (host port). the igmp packets are identified as ip packets (e ither ethernet ip packets, or ieee 802.3 snap ip packets ) with ip version = 0x4 and protocol version number = 0x2. ?multicast address insertion? in the static mac table once the multicast address is programmed in the static mac table, the multicast session is trimmed to the subscribed ports, instead of broadcasting to all ports. ipv6 mld snooping the ksz8842-pmql/pmbl traps ipv6 multicast listener disc overy (mld) packets and forwards them only to the processor (host port). mld snooping is controlled by sg cr2[13] (mld snooping enable) and sgcr2[12] (mld option). setting sgcr2[13] causes the ksz8842-pmql/pmbl to trap packets that meet all of the following conditions: ? ipv6 multicast packets ? hop count limit = 1 ? ipv6 next header = 1 or 58 (or = 0 with hop-by-hop next header = 1 or 58) ? if sgcr2[12] =1, ipv6 next header = 43, 44, 50, 51, or 60 (or =0 with hop-by-hop next header = 43, 44, 50, 51, or 60) port mirroring support ksz8842-pmql/pmbl supports ?port mirroring? comprehensively as: ?receive only? mirror on a port all the packets received on the port are mirrored on the sni ffer port. for example, port 1 is programmed to be ?receive sniff? and the host port is programmed to be the ?sniffer port?. a packet received on port 1 is destined to port 2 after the internal lookup. the ksz8842-pmql/pmbl forwards the packet to both port 2 and the host port. the ksz8842- pmql/pmbl can optionally even forward ?bad? received packets to the ?sniffer port?. ?transmit only? mirror on a port all the packets transmitted on the port are mirrored on the sniffer port. for example, port 1 is programmed to be ?transmit sniff? and the host port is programmed to be the ?s niffer port?. a packet received on port 2 is destined to port 1
micrel, inc. ksz8842-pmql/pmbl october 2007 31 m9999-100207-1. 5 after the internal lookup. the ksz8842-pmql/pmbl fo rwards the packet to both port 1 and the host port. ?receive and transmit? mirror on two ports all the packets received on port a and transmitted on port b are mirrored on the sniffer port. to turn on the ?and? feature, set register sgcr2, bit 8 to ?1?. for example, port 1 is programmed to be ?receive sniff?, port 2 is programmed to be ?transmit sniff?, and the host port is programmed to be the ?sniffer port?. a packet rece ived on port 1 is destined to port 2 after the internal lookup. the ksz8842-pmql/pmbl forwards the packet to both port 2 and the host port. multiple ports can be selected as ?receive sniff? or ?transmit sniff?. in addition, any port can be selected as the ?sniffer port?. all these per port features can be selected through registers p1cr2, p2cr 2, and p3cr2 for ports 1, 2, and the host port, respectively. ieee 802.1q vlan support the ksz8842-pmql/pmbl supports 16 acti ve vlans out of the 4096 possible vlans specified in the ieee 802.1q specification. ksz8842-pmql/pmbl provides a 16-entry vlan table, which conver ts the 12-bits vlan id (vid) to the 4-bits filter id (fid) for address lookup. if a non-tagged or nul l-vid-tagged packet is receiv ed, the ingress port default vid is used for lookup. in vlan mode, the lookup process starts with vlan table lookup to determine whether the vid is valid. if the vid is not valid, the packet is dropped and it s address is not learned. if the vid is valid, the fid is retrieved for further lookup. the fid + destination addres s (fid+da) are used to deter mine the destination port. the fid + source address (fid+sa) are used fo r address learning. (see tables 12 and 13.) da found in static mac table? use fid flag? fid match? da+fid found in dynamic mac table? action no don?t care don?t care no broadcast to the membership ports defined in the vlan table bits [18:16] no don?t care don?t care yes send to the destination port defined in the dynamic mac address table bits [53:52] yes 0 don?t care don?t care send to the destination port(s) defined in the static mac addres s table bits [50:48] yes 1 no no broadcast to the membership ports defined in the vlan table bits [18:16] yes 1 no yes send to the destination port defined in the dynamic mac address table bits [53:52] yes 1 yes don?t care send to the destination port(s) defined in the static mac addres s table bits [50:48] table 5. fid+da lookup in vlan mode fid+sa found in dynamic mac table? action no learn and add fid+sa to the dynamic mac address table yes update time stamp table 6. fid+sa lookup in vlan mode qos priority support the ksz8842-pmql/pmbl provides quality of service (qos ) for applications such as voip and video conferencing. offering four priority queues per port, the per-port transmit queue can be split into four priority queues: queue 3 is the highest priority queue and queue 0 is the lowest priority queue. bit 0 of registers p1cr 1, p2cr1, and p3cr1 is used to enable split transmit queues for ports 1, 2, and the host port, respectively. port-based priority with port-based priority, each ingress port can be individually classified as a hi gh-priority receiving port. all packets
micrel, inc. ksz8842-pmql/pmbl october 2007 32 m9999-100207-1. 5 received at the high-priority receiving port are marked as hi gh priority and are sent to the high-priority transmit queue if the corresponding transmit queue is split. bit 4 and 3 of r egisters p1cr1, p2cr1, and p3cr1 is used to enable port- based priority for ports 1, 2, and the host port, respectively. 802.1p-based priority for 802.1p-based priority, the ksz8842-pmql/pmbl examines the ingress (incoming) packets to determine whether they are tagged. if tagged, the 3-bit priority field in the vlan tag is re trieved and compared against the ?priority mapping? value, as specified by the register sgcr 6. the ?priority mapping? value is programmable. figure 9 illustrates how the 802.1p priority fi eld is embedded in the 802.1q vlan tag. preamble da tci 766 2 length data fcs 2 46-1500 4 s f d 1 tagged packet type (8100 for ethernet) 802.1p cfi vlan id bytes bits 16 3 12 802.1q vlan tag 2 sa vpid 1 figure 9. 802.1p priority field format 802.1p based priority is enabled by bit 5 of registers p1cr1, p2cr1, and p3cr 1 for ports 1, 2, and the host port, respectively. the ksz8842-pmql/pmbl provides the option to insert or re move the priority tagged frame's header at each individual egress port. this header, consisting of the 2 bytes vlan protoc ol id (vpid) and the 2 bytes tag control information field (tci), is also referred to as the 802.1q vlan tag. tag insertion is enabled by bit 2 of registers p1cr1, p2cr1, and p3 cr1 for ports 1, 2, and the host port, respectively. at the egress port, untagged packets are tagged with the ingres s port?s default tag. the defau lt tags are programmed in register sets p1vidcr, p2 vidcr, and p3vidcr for po rts 1, 2 and the host port, respectively. the ksz8842- pmql/pmbl does not add tags to already tagged packets. tag removal is enabled by bit 1 of registers p1cr1, p2cr1, and p3cr1 for ports 1, 2, and the host port, respectively. at the egress port, tagged pac kets will have their 802.1q vlan tags removed. the ksz8842-pmql/pmbl will not modify untagged packets. the crc is recalculated for both tag insertion and tag removal. 802.1p priority field re-mapping is a qos feature that allows the ksz8842-pmql/pmbl to set the ?user priority ceiling? at any ingress port. if the ingres s packet?s priority field has a higher pr iority value than the default tag?s priorit y field of the ingress port, the packet?s priority field is replac ed with the default tag?s priority field. the ?user priority ceiling? is enabled by bit 3 of regist ers p1cr2, p2cr2, and p3cr 2 for ports 1, 2, and the host port, respectively. diffserv based priority diffserv-based priority uses the tos regi sters shown in the priority control regi sters section. the tos priority control registers implement a fully decoded, 128 -bit differentiated services code poin t (dscp) register to determine packet priority from the 6-bit tos field in the ip header. when the mo st significant 6 bits of the tos field are fully decoded, the resultant of the 64 possibilities is comp ared with the corresponding bi ts in the dscp register to determine priority. rate limiting support the ksz8842-pmql/pmbl supports hardware rate limiting from 64 kbps to 88 mbps, independently on the ?receive side? and on the ?transmit side? on a per port basis. for 10b ase-t, a rate setting above 10 mbps means the rate is not limited. on the receive side, the data re ceive rate for each priority at each por t can be limited by setting up ingress rate control registers. on the tr ansmit side, the data transmit rate for each priority queue at each port can be limited by setting up egress rate control registers. the size of eac h frame has options to include minimum ifg (inter frame gap) or preamble byte, in addition to th e data field (from packet da to fcs).
micrel, inc. ksz8842-pmql/pmbl october 2007 33 m9999-100207-1. 5 for ingress rate limiting, ksz8842-pmql/pmbl provides options to selectively choose frames from all types, multicast, broadcast, and flooded unicast frames. the ksz8842-pmql/p mbl counts the data rate from those selected type of frames. packets are dropped at the ingress port when the data rate exceeds the specified rate limit. for egress rate limiting, the leaky bucket algorithm is app lied to each output priority queue for shaping output traffic. inter frame gap is stretched on a per frame base to generat e smooth, non-bursty egress traffic. the throughput of each output priority queue is limited by the egress rate specified. if any egress queue receives more traffic than the specified egress rate throughput, packets may be accumulated in the output queue and packet memory. after the memory of the queue or the port is used up, packet dropping or flow control will be triggered. as a result of congest ion, the actual eg ress rate may be do minated by flow control/dropping at the ingress end, and may be therefore slightly less than the specified egress rate. to reduce congestion, it is a good practice to make su re the egress bandwidth exceeds the ingress bandwidth. mac filtering function use the static table to assign a dedicated mac address to a specific po rt. when a unicast mac address is not recorded in the static table, it is also not learned in the dynamic mac table. the ksz8842-pmql/pmbl includes an option that can filter or forward unicast packets for an unknown mac address. this option is enabled by sgcr7[7]. the unicast mac address filtering function is useful in preventing the broadcast of unicast packets that could degrade the quality of this port in applications such as voice over internet protocol (voip). configuration interface the ksz8842-pmql/pmbl operates as a managed switch or a repeater, however it cannot be used as an unmanaged switch. eeprom interface the external serial eeprom with a standard microwire bus interface is used for non-volat ile storage of information such as the host mac addres s and id, (for example, 93c46 or 93c66 eeprom devices.) if the eeen pin/ball is pulled high, the ksz8842-pmql/pmbl performs an autom atic read of the external eeprom words 0h to 6h after the de-assertion of reset. the eeprom values are placed in certain host-accessible registers. eeprom read/write fu nctions can also be performed by softwar e read/writes to t he eepcr registers. the ksz8842-pmql/pmbl eeprom format is given below. word 15 8 7 0 0h reserved 1h host mac address byte 2 host mac address byte 1 2h host mac address byte 4 host mac address byte 3 3h host mac address byte 6 host mac address byte 5 4h subsystem id 5h subsystem vendor id 6h reserved 7h-3fh not used by ksz8842-pmql/pmbl (available for user to use) table 7. eeprom format loop back support the ksz8842-pmql/pmbl provides loop back support for remo te diagnostic of failure. in loop back mode, the speed at both phy ports will be set to 100base- tx full-duplex mode. two types of loop back are suppo rted: far-end loop back and near-end (remote) loop back. far-end loop back: far-end loop back is conducted between the ksz8842-pmql/p mbl?s two phy ports. the loop back path starts at the ?originating? phy. the originating phy port?s receive input s (rxp/rxm), wrap around at the ?loop back? phy port?s pmd/pma, and ends at the ?originating? phy port?s transmit outputs (txp/txm).
micrel, inc. ksz8842-pmql/pmbl october 2007 34 m9999-100207-1. 5 bit [8] of registers p1cr4 and p2cr4 is used to enable far-en d loop back for ports 1 and 2, respectively. alternatively, bit [14] of registers p1mbcr and p2mb cr can also be used to enable far-end loop back. when register p2mbcr bit 14 =1 or p2cr4 bit 8 =1, the port 2 far-end loop back path is illustrated in the figure 11. near-end (remote) loop back: near-end (remote) loop back is conducted at either phy po rt 1 or phy port 2 of the ksz8842-pmql/pmbl. the loop back path starts at the phy port?s rece ive inputs (rxpx/rxmx), wraps around at the same phy port?s pmd/pma, and ends at the phy port?s transmit outputs (txpx/txmx). bit [1] of registers p1phyctrl and p2phyctrl is used to enable near-end loop back for ports 1 and 2, respectively. alternatively, bit [9] of registers p1scslmd and p2sc slmd can also be used to enable near-end loop back. both ports 1 and 2 near-end loop back paths are illustrated in the following figure 10. pm d2/pm a2 pcs2 mac2 sw itch mac1 pcs1 pm d1/pm a1 o r ig in a tin g ph y port 1 ph y port 2 f ar-end l oop b ack rxp1 / rxm 1 txp1 / txm 1 figure 10. port 2 far-end loop back path pm d2/pm a2 pcs2 mac2 switch mac1 pcs1 pm d1/pm a1 rxp rxp rxp rxp1 1 1 1 / // / rxm rxm rxm rxm 1 1 1 1 txp txp txp txp1 1 1 1 / // / txm txm txm txm 1 1 1 1 txp txp txp txp 2 2 2 2 / // / txm txm txm txm 2 2 2 2 rxp rxp rxp rxp2 2 2 2 / // / rxm rxm rxm rxm 2 2 2 2 phy port phy port phy port phy port 2 2 2 2 n ear n ear n ear n ear- - - -end end end end ( ( ( (rem ote re m o te re m o te re m o te ) ) ) ) loopback loopback loopback loopback phy port phy port phy port phy port 1 1 1 1 near near near near- - - -e n d end end end ( ( ( (rem ote re m o te re m o te re m o te ) ) ) ) loopback loopback loopback loopback figure 11. port 1 and port 2 near-end (remote) loop back path
micrel, inc. ksz8842-pmql/pmbl october 2007 35 m9999-100207-1. 5 host communication the descriptor lists and data buffers, collectively called the host communication, manage the actions and status related to rx and tx buffer management. commands and signals that control the functional operation of the ksz8842- pmql/pmbl are also described. the ksz8842-pmql/pmbl and the driver communicate th rough the two data structur es: command and status registers (csrs), and descriptor lists and data buffers. note: all unused bits of the data structure in this secti on are reserved and should be written by the driver as zero. host communication descriptor lists and data buffers the ksz8842-pmql/pmbl transfers received data frames to the receive buffer in host memory and transmits data from the transmit buffers in host memory . descriptors that reside in the host memo ry act as pointers to these buffers. there are two descriptor lists (one for receive and one for tr ansmit) for mac dma. the base address of each list is written in the tdlb register and in the rdlb register, respectively. a descriptor li st is forward linked. the last descriptor may point back to the first entry to create a ring structure. descriptors ar e chained by setting the next address to the next buffer in both the receive and transmit descriptors. the descriptor lists reside in the host physical memory address space. each pointer points to one buffer and the second pointer points to the next descriptor. this enables t he greatest flexibility for the host to chain any data buffers with discontinuous memory location. this eliminates processo r-intensive tasks such as me mory copying from the host to memory. a data buffer contains either an entire frame or part of a fr ame, but it cannot exceed a singl e frame. buffers contain only data; and buffer status is maintained in the descriptor. data chaining refers to frames that span multiple data buffers. data chaining can be enabled or disabled. data buffers reside in host physical memory space. receive descriptors (rdes0-rdes3) receive descriptor and buffer addresses must be word align ed. each receive descriptor provides one frame buffer, one byte count field, and control and status bits. the following table shows the rdes0 register bit fields. bit description 31 own own bit when set, indicates that the descriptor is owned by the ksz8842-pmql/pmbl. when reset, indicates that the descriptor is owned by the host. the ksz8842-pmql/pmbl clears this bit either when it completes the frame reception or when the buffers that are associated with this descriptor are full. 30 fs first descriptor when set, indicates that this descriptor contains the first buffer of a frame. if the buffer size of the first buffer is 0, t he next buffer contains the beginning of the frame. 29 ls last descriptor when set, indicates that the buffer pointed by this descriptor is the last buffer of the frame. 28 ipe ip checksum error when set, indicates that the received frame is an ip packet and its ip checksum field does not match. this bit is valid only when last descriptor is set. 27 tcpe tcp checksum error when set, indicates that the received frame is a tcp/ip packet and its tcp checksum field does not match. this bit is valid only when last descriptor is set. 26 udpe udp checksum error when set, indicates that the received frame is an udp/ip packet and its udp checksum field does not match. this bit is valid only when last descriptor is set.
micrel, inc. ksz8842-pmql/pmbl october 2007 36 m9999-100207-1. 5 bit description 25 es error summary indicates the logical or of the following rdes0 bits: crc error frame too long runt frame this bit is valid only when last descriptor is set. 24 mf multicast frame when set, indicates that this frame has a multicast address. this bit is valid only when last descriptor is set. 23 ? 20 spn switch engine source port number this field indicates the source port where the packet originated. if bit 20 is set, it indicates the packet was received from port 1. if bit 21 is set, it indicates the packet was received from port 2. this field is valid only when the last descriptor is set. (bits 23 and 22 are not used, but reserved for bac kward compatibility and future expansion.) 19 re report on mii error when set, indicates that a receive error in the physical layer was reported during the frame reception. 18 tl frame too long when set, indicates that the frame length exceeds the maximum size of 1518 bytes. this bit is valid only when last descriptor is set. note: frame too long is only a frame length indication and does not cause any frame truncation. 17 rf runt frame when set, indicates that this frame was dam aged by a collision or premature termination before the collision window has passed. runt fr ames are passed on to the host only if the pass bad frame bit is set. 16 ce crc error when set, indicates that a crc error occurred on the received frame. this bit is valid only when last descriptor is set. 15 ft frame type when set, indicates that the frame is an ether net-type frame (frame length field is greater than 1500 bytes). when clear, indicates t hat the frame is an ieee 802.3 frame. this bit is not valid for runt frames. this bit is valid only when last descriptor is set. 14 ? 11 reserved 10 ? 0 fl frame length indicates the length, in bytes, of the received frame, including the crc. this field is valid only when last descriptor is set and descriptor error is reset.
micrel, inc. ksz8842-pmql/pmbl october 2007 37 m9999-100207-1. 5 the following table shows the rdes1 register bit fields. bit description 31 ? 26 reserved 25 rer receive end of ring when set, indicates that the descriptor list reached its final descriptor. the ksz8842- pmql/pmbl returns to the base address of the list, thus creating a descriptor ring. 24 ? 11 reserved 10 ? 0 rbs receive buffer size indicates the size, in bytes, of the rece ive data buffer. if the field is 0, the ksz8842- pmql/pmbl ignores this buffer and moves to the next descriptor. the buffer size must be a multiple of 4. the following table shows the rdes2 register bit fields. bit description 31 ? 0 buffer address indicates the physical memory address of the buffer. the buffer address must be word aligned. the following table shows the rdes3 register bit fields. bit description 31 ? 0 next descriptor address indicates the physical memory address of th e next descriptor in the descriptor ring. the buffer address must be word aligned. transmit descriptors (tdes0-tdes3) transmit descriptors must be word aligned. each descrip tor provides one frame buffer, one byte count field, and control and status bits. the following table shows the tdes0 register bit fields. bit description 31 own own bit when set, indicates that the descriptor is owned by the ksz8842-pmql/pmbl. when cleared, indicates that the descriptor is owned by the host. the ksz8842-pmql/pmbl clears this bit either when it completes the fr ame transmission or when the buffer allocated in the descriptor is empty. the ownership bit of the first descriptor of the frame should be set after all subsequent descriptors belonging to the same frame have been set. this avoids a possible race condition between the ksz8842-pmql/pmbl fetchi ng a descriptor and the driver setting an ownership bit. 30 ? 0 reserved the following table shows the tdes1 register bit fields. bit description 31 ic interrupt on completion when set, the ksz8842-pmql/pmbl sets transmit interrupt after the present frame has been transmitted. it is valid only when last segment is set. 30 fs first segment when set, indicates that the buffer cont ains the first segment of a frame. 29 ls last segment when set, indicates that the buffer cont ains the last segment of a frame.
micrel, inc. ksz8842-pmql/pmbl october 2007 38 m9999-100207-1. 5 bit description 28 ipckg ip checksum generate when set, the ksz8842-pmql/pmbl will generate correct ip checksum for outgoing frames that contains ip protocol header. the ksz 8842-pmql/pmbl supports only a standard ip header, i.e., ip with a 20 byte header. when t his feature is used, add crc bit in the transmit mode register should always be set. this bit is used as a per-packet control when the ip checksum generate bit in the transmit mode register is not set. this bit should be always set for multiple-segment packets. 27 tcpckg tcp checksum generate when set, the ksz8842-pmql/pmbl will generate correct tcp checksum for outgoing frames that contains ip and tcp protocol header. the ksz8842-pmql/pmbl supports only a standard ip header, i.e., ip with a 20 byte hea der. when this feature is used, add crc bit in the transmit mode register should always be set. this bit is used as a per-packet control when the tcp checksum generate bit in the transmit mode register is not set. this bit should be always set for multiple-segment packets. 26 udpckg udp checksum generate when set, the ksz8842-pmql/pmbl will generate correct udp checksum for outgoing frames that contains a ip and udp pr otocol header. the ksz8842-pmql/pmbl supports only a standard ip header, i.e., ip with a 20 byte header. when this feature is used, add crc bit in the transmit mode register should always be set. this bit is used as a per-packet control when the udp checksum generate bit in the transmit mode register is not set. 25 ter transmit end of ring when set, indicates that the descriptor po inter has reached its final descriptor. the ksz8842-pmql/pmbl returns to the base addr ess of the list, forming a descriptor ring. 24 reserved 23 ? 20 spn switch engine destination port map when set, this field indicates the destination port(s) where the packet will be forwarded to. if bit 20 is set, it indicates the packet was received from port 1. if bit 21 is set, it indicates the packet was received from port 2. setting all ports to 1 will cause the switch engine to broadcast the packet. setting all bits to 0 has no effect. the switch engine forwards the packet according to its internal switch lookup algorithm. this field is valid only when the last descriptor is set. (bits 23 and 22 are not used, but reserved for backward compatibility and future expansion.) 19 ? 11 reserved 10 ? 0 tbs transmit buffer size indicates the size, in bytes, of the transmit data buffer. if this field is 0, the ksz8842-pmql/pmbl ignor es this buffer and moves to the next descriptor. the following table shows the tdes2 register bit fields. bit description 31 - 0 buffer address indicates the physical memory address of the buffer. there is no limitation on the transmit buffer address alignment.
micrel, inc. ksz8842-pmql/pmbl october 2007 39 m9999-100207-1. 5 the following table shows the tdes3 register bit fields. bit description 31 - 0 next descriptor address indicates the physical memory address of th e next descriptor in the descriptor ring. the buffer address must be word aligned. pci configuration registers the ksz8842-pmql/pmbl implements 12 configuration regist ers. these registers are described in the following subsections. the ksz8842-pmql/pmbl enables a full software-driven initializ ation and configuration. th is allows the software to identify and query the ksz8842-pmql/pmbl. the ksz8842-pmql/ pmbl treats configuration space write operations to registers that are reserved as no-ops. that is, the acce ss completes normally on the bus and the data is discarded. read accesses, to reserved or unimp lemented registers, complete normally and a data value of 0 is returned. software reset has no effect on the confi guration registers. hardware reset sets the configuration registers to their default values. configuration register identifier i/o address offset default identification cfid 00h 0x884116c6 command and status cfcs 04h 0x02000000 revision cfrv 08h 0x02000010 latency timer cflt 0ch 0x00000000 base memory address cbma 10h 0x00000000 reserved ? 14h-28h 0x00000000 subsystem id csid 2ch 0x******** reserved ? 38h 0x00000000 interrupt cfit 3ch 0x28140100 reserved ? 40h-4ch 0x00000000 configuration id register (cfid offset 00h) the cfid register identifies the ksz8842-pmql/pmbl. t he following table shows the cfid register bit fields. bit default description 31 - 16 0x8842 device id 15 - 0 0x16c6 vendor id specifies the manufacturer of the ksz8842-pmql/pmbl. the following table shows the ac cess rules of the register. command and status configuration register (cfcs offset 04h) the cfcs register is divided into two sections: a command register (cfcs[15:0]) and a stat us register (cfcs[31:16]). the command register provides contro l of the ksz8842-pmql/pmbl?s ability to generate and respo nd to pci cycles. when 0 is written to this register, the ksz8842-pmql/pmbl logically disconne cts from the pci bus for all accesses except configuration accesses. the status register records status information for the pci bus-related ev ents. the cfcs status bits are not cleared when they are read. writing 1 to these bi ts clears them; writing 0 has no effect. category description value after hardware reset 0x884216c6 write access rules write has no effect on the ksz8842-pmql/pmbl.
micrel, inc. ksz8842-pmql/pmbl october 2007 40 m9999-100207-1. 5 the following table describes the cfcs register bit fields. bit type default description 31 status 0 detected parity error when set, indicates that the ksz8842-pmql/pmbl detected a parity error, even if parity error handling is disabled in parity error response (cfcs[6]). 30 status 0 signal system error when set, indicates that the ksz8842-pmql/pmbl asserted the system error serr_n pin/ball. 29 status 0 received master abort when set, indicates that the ksz8842-pmql/pmbl terminated a master transaction with master abort. 28 status 0 received target abort when set, indicates that the ksz8842-pmql/pmbl master transaction was terminated due to a target abort. 27 status 0 target abort this bit is set by ksz8842-pmql/pmbl whenever it terminates with a target abort. the csr registers are all 32-bit little endian format. for pci register read cycles, the ksz8842-pmql/pmbl allows any different combination of cben. for pci register bus cycles, only byte, word (16-bit), or dword (32-bit) accesses are allowed. any other combination is ill egal and is target aborted. 26 ? 25 status 01 device select timing indicates the timing of the asse rtion of device select(devsel_n). these bits are fixed at 01, which indicates a middle assertion of devsel_n. 24 status 0 data parity report this bit is set when the following conditions are met: the ksz8842-pmql/pmbl asserts parity error perr_n or it senses the assertion of perr_n by another device. the ksz8842-pmql/pmbl operates as a bus master for the operation that caused the error. parity error response (cfcs[6]) is set. 23 ? 22 reserved 00 reserved 21 status 0 66mhz capable 0 = not 66mhz capable 20 ? 9 reserved 0x000 reserved 8 command 0 system error enable when set, the ksz8842-pmql/pmbl asserts system error (serr_n) when it detects a parit y error on the address phase. 7 reserved 0 reserved 6 command 0 parity error response when set, the ksz8842-pmql/pmbl asserts fatal bus error after it detects a parity error. when reset, any detected parity error is ignored and the ksz8842- pmql/pmbl continues normal operation. parity checking is disabled after hardware reset. 5 ? 3 reserved 000 reserved
micrel, inc. ksz8842-pmql/pmbl october 2007 41 m9999-100207-1. 5 bit type default description 2 command 0 master operation when set, the ksz8842-pmql/pmbl is capable of acting as a bus master. when reset, the ksz8842-pmql/pmbl capability to generate pci accesses is disabled. for normal operation, this bit must be set. 1 command 0 memory space access when set, the ksz8842-pmql/pmbl responds to memory space accesses. when reset, the ksz8842-pmql/pmbl does not respond to memory space accesses. 0 reserved 0 reserved configuration revision register (cfrv offset 08h) the cfrv register contains the ksz8842-pmql/pmbl revisi on number. the following table shows the cfrv register bit fields. bit default description 31 ? 24 0x02 base class indicates the network controller, and is equal to 2h. 23 ? 16 0x00 subclass indicates the fast/gigabit ethernet chip, and is equal to 00h. 15 ? 8 0x00 reserved 7 ? 4 0x1 revision number indicates the ksz8842-pmql/pmbl revision number, and is equal to 1h. this number is incremented for subsequent revision. 3 ? 0 0x0 step number indicates the ksz8842-pmql/pmbl step number, and is equal to 0h (chip revision a). this number is incremented for subsequent ksz8842- pmql/pmbl steps within the current revision. configuration latency timer register (cflt offset 0ch) this register configures the cache line size field and the latency timer. the following table shows the cflt register bit fields. bit default description 31 ? 16 0x00 reserved 15 ? 8 0x00 configuration latency timer specifies, in units of pci bus clocks, the value of the latency timer of the ksz8842-pmql/pmbl. when the ksz8842-pmql/pmbl asserts frame_n, it enables its latency timer to count. if the ksz8842-pmql/pmbl deasserts frame_n prior to count expiration, the co ntent of the latency timer is ignored. otherwise, after the count expires, the ksz8842-pmql/pmbl initiates transaction termination as soon as its gnt_n is deasserted. 7 ? 0 0x00 cache line size specifies, in unit of 32-bit words (d word), the system cache line size.
micrel, inc. ksz8842-pmql/pmbl october 2007 42 m9999-100207-1. 5 configuration base memory address register (cbma offset 10h) the cbma register specifies the base memory address for accessing the ksz 8842-pmql/pmbl csrs. this register must be initialized prior to accessing any csr with memory access. the following table shows the cbma register bit fields. bit default description 31 - 11 0 configuration base memory address defines the base address assigned for mapping the ksz8841-pmql/pmbl csrs. 10 - 1 0 this field value is 0 when read. 0 0 memory space indicator determines that the register maps into the memory space. the value in this field is 0. this is a read-only field. subsystem id register (csid offset 2ch) the csid register is a read-only 32-bit register. the content of the csid is loaded from the eeprom after a hardware reset. the loading period lasts at least 27,400 pci cycles when the system is in 33mhz mode, and starts 50 cycles after hardware reset deassertion. if th e host accesses the csid before its co ntent is loaded from the eeprom, the ksz8842-pmql/pmbl responds with retry termination on the pci bus. the following table shows the csid register bit fields. bit description 31 ? 16 subsystem id indicates a 16-bit field containing the subsystem id. 15 ? 0 subsystem vendor id indicates a 16-bit field containing the subsystem vendor id. the following table shows the ac cess rules of the register. configuration interrupt register (cfit offset 3ch) the cfit register is divided into two sections: the interr upt line and the interrupt pin/ba ll. cfit configures both the system?s interrupt and the ksz8842-pmql/ pmbl interrupt pin/ball connection. the following table shows the cfit register bit fields. bit default description 31 ? 24 0x28 max_lat this field indicates how often the device needs to gain access to the pci bus. time unit is equal to 0.25s, assuming a pci clock frequency of 33 mhz. the value after a hardware reset is 28h (10s). 23 ? 16 0x14 min_gnt this field indicates the burst period lengt h that the device needs. time unit is equal to 0.25s, assuming a pci clock frequency of 33 mhz. the value after a hardware reset is 14h (5s). 15 ? 8 0x01 interrupt pin/ball indicates which interrupt pin/ball that the ksz8842-pmql/pmbl uses. the ksz8842-pmql/pmbl uses inta# and the read value is 1h. category description value after hardware reset read from eeprom. write access rules write has no effect on the ksz8842-pmql/pmbl.
micrel, inc. ksz8842-pmql/pmbl october 2007 43 m9999-100207-1. 5 bit default description 7 ? 0 0x00 interrupt line provides interrupt line routing informa tion. the basic input/output system (bios) writes the routing information into to this field when it initialized and configures the system. the value in this field indicates which input of the system interrupt controller is connected to the ksz8842-pmql/pmbl?s int errupt pin/ball. the driver uses this information to determine priority and vector information. values in this field are system architecture specific. the following table shows the ac cess rules of the register. category description value after hardware reset 0x281401xx pci control & status registers the pci csr registers are all 32 bit in little endian form at. for pci register read cycle, the ksz8842-pmql/pmbl allows any different combination of c ben. for pci register bus cycles, only by te, word (16-bit), or dword (32-bit) accesses are allowed. any other combinations are illegal , and will be target aborted. mac dma transmit control register (mdtxc offset 0x0000) the mac dma transmit control register establishes the transmit operating modes and commands for the port. this register should be one of the last csrs to be wr itten as part of the transmit initialization. the following table shows the register bit fields. bit default r/w description 31 ? 30 - ro reserved 29 ? 24 0x00 rw mtbs dma transmit burst size this field indicates the maximum number of words to be transferred in one dma transaction. if reset, the mac dma burst size is limited only by the amound of data stored in the transmit bu ffer before issuing a bus request. the mtbs can be programmed with the following permissible values: 0,1, 2, 4, 8, 16, or 32. after reset, the mtbs default is 0, i.e., unlimited. 23 ? 19 0x00 ro reserved 18 0 rw mtucg mac transmit udp checksum generate when set, the ksz8842-pmql/pmbl will generate correct udp checksum for outgoing udp/ip frames at port. when this bit is set, add crc should also turn on. 17 0 rw mttcg mac transmit tcp checksum generate when set, the ksz8842-pmql/pmbl will generate correct tcp checksum for outgoing tcp/ip frames at port. when this bit is set, add crc should also turn on. 16 0 rw mticg mac transmit ip checksum generate when set, the ksz8842-pmql/pmbl will generate correct ip checksum for outgoing ip frames at port. when this bit is set, add crc should also turn on. 15 ? 10 0x00 ro reserved
micrel, inc. ksz8842-pmql/pmbl october 2007 44 m9999-100207-1. 5 bit default r/w description 9 0 rw mtfce mac transmit flow control enable when this bit is set, flow control is enabled. this causes the ksz8842- pmql/pmbl to transmit a pause frame from dma to switch host mac when the receive buffer has reached threshold and this bit is enabled. (sgcr3 bit 5 also needs to be enabled). note: ksz8842-pmql/pmbl is full duplex only for rx/tx buffer. 8 ? 3 0x0 ro reserved 2 0 rw mtep mac dma transmit enable padding when set, the ksz8842-pmql/pmbl automat ically adds a padding field to a packet shorter than 64 bytes. note: setting this bit automatically enables add crc feature. 1 0 rw mtac mac dma transmit add crc when set, the ksz8842-pmql/pmbl appen ds the crc to the end of the transmission frame. 0 0 rw mte mac dma tx enable when the bit is set, the mdma tx block is enabled and placed in a running state. when reset, the transmission process is placed in the stopped state after completing the transmission of t he current frame. the stop transmission command is effective only when the tr ansmission process is in the running state. mac dma receive control register (mdrxc offset 0x0004) the mac dma receive control register establishes t he receive operating modes and commands for the port. this register should be one of the last csrs to be written as part of the receive initialization. the following table shows the register bit fields. bit default r/w description 31 ? 30 00 ro reserved 29 ? 24 0x00 rw mrbs dma receive burst size this field indicates the maximum number of words to be transferred in one dma transaction. if reset, the mac dma burst size is limited only by the amount of data stored in the receive buffer before issuing a bus request. the mrbs can be programmed with the following permissible values: 0,1, 2, 4, 8, 16, or 32. after reset, the mrbs default is 0, i.e., unlimited. 23 ? 19 0x0 ro reserved 18 0 rw mrucc mac receive udp checksum check when set, the ksz8842-pmql/pmbl will check for correct udp checksum for incoming udp/ip frames at port. packets received with incorrect udp checksum will be discarded. 17 0 rw mrtcg mac receive tcp checksum check when set, the ksz8842-pmql/pmbl will check for correct tcp checksum for incoming tcp/ip frames at port. packets received with incorrect tc p checksum will be discarded. 16 0 rw mricg mac receive ip checksum check when set, the ksz8842-pmql/pmbl will check for correct ip checksum for incoming ip frames at port. packets received with incorrect ip checksum will be discarded.
micrel, inc. ksz8842-pmql/pmbl october 2007 45 m9999-100207-1. 5 9 0 rw mrfce mac receive flow control enable when set, flow control is enabled. the ksz8842-pmql/pmbl will acknowledge a pause frame from the sw itch, the outgoing packets will be pending in the transmit buffer until the pause control timer expires. when this bit is cleared, no flow control is enabled. note: ksz8842-pmql/pmbl is full duplex only for rx/tx buffer. 8 ? 7 00 ro reserved 6 0 rw mrb mac receive broadcast when set, the mac receive all broadcast frames. 5 0 rw mrm mac receive multicast when set, the mac receive all multicast frames (including broadcast). 4 0 rw mru mac receive unicast when set, the mru mac receive unicast frames that match the 16 48-bit mac additional station address and the mac address register if they are set by user. 3 0 rw mre mac dma receive error frame when set, the ksz8842-pmql/pmbl will pass the errors frames received to the host. error frames include runt frames, oversized frames, crc errors. 2 0 rw mra mac dma receive all when set, the ksz8842-pmql/pmbl will receive all incoming frames, regardless of its destination address. 1 0 rw dma receive multicast hash-table enable when set, the rx function to receive multicast frames that pass the crc hash filtering mechanism. 0 0 rw mre mac dma rx enable when set, the dma rx block is enabled and placed in a running state. when reset, the receive process is placed in the stopped state after completing the reception of the current frame. the stop transmission command is effectiv e only when the reception process is in the running state. mac dma transmit start command register (mdtsc offset 0x0008) this register is written by the cpu when pac kets in the data buffer need to be transmitted. the following table shows the register bit fields. bit default r/w description 31 ? 0 0x00000000 wo wtsc transmit start command when written with any value, the transmit dma checks for frames to be transmitted. if no descriptor is available, the transmit process returns to suspended state. if descriptiors are avai lable, the transmit process starts or resumes. this bit is self-clearing.
micrel, inc. ksz8842-pmql/pmbl october 2007 46 m9999-100207-1. 5 mac dma receive start command register (mdrsc offset 0x000c) this register is written by t he cpu when there are frame data in receive buffer to be processed. the following table shows the register bit fields. bit default \ r/w description 31 ? 0 0x00000000 wo wrsc receive start command when written with any value, the receive dma checks for descriptors to be acquired. if no descriptor is available, the receive process returns to suspended state and waits for the next receive restart command. if descriptiors are available, the receive process resumes. this bit is self-clearing. transmit descriptor list base address register (tdlb offset 0x0010) this register is used for the transmit descriptor list base address. the register is used to point to the start of the appropriate descriptor list. writing to this register is permi tted only when its respective pr ocess is in the stopped state. when stopped, the register must be written before the respective start command is given. note: the descriptor lists must be wo rd (32-bit) aligned. the ksz8842-pmql/ pmbl behavior is unpredictable when the lists are not word-aligned. the following table shows the register bit fields. bit default r/w description 31 ? 0 0x0 rw wstl start of transmit list note: write can only occur when t he transmit process stopped. receive descriptor list base address register (rdlb offset 0x0014) this register is used for the receive descriptor list base address. the register is used to point to the start of the appropriate descriptor list. writing to this register is permi tted only when its respective pr ocess is in the stopped state. when stopped, the register must be written before the respective start command is given. note: the descriptor lists must be wo rd (32-bit) aligned. the ksz8842-pmql/ pmbl behavior is unpredictable when the lists are not word-aligned . the following table shows the register bit fields. bit default read/ write description 31 ? 0 0x0 rw wsrl start of receive list note: write can only occur when t he transmit process stopped. reserved (offset 0x0018) the following table shows the register bit fields. bit default r/w description 31 ? 0 0x0 ro reserved reserved (offset 0x001c) the following table shows the register bit fields. bit default r/w description 31 ? 0 0x0 ro reserved mac multicast table 0 register (mtr0 offset 0x0020) the 64 bit multicast table is used for group address filtering. t he hash value is defined as the six most significant bits of the crc of the da. the two most significant bits select the register to be used, while the other determines the bit within the register.
micrel, inc. ksz8842-pmql/pmbl october 2007 47 m9999-100207-1. 5 the following table shows the register bit fields. bit default r/w description 31 ? 0 0x0 rw mtr0 multicast table 0 when appropriate bit is set, the packet received with da matches the crc hashing function is received without being filtered. note: when the receive all (rxra) or receive multicast (rxrm) bit is set in the rxcr then all multicast addresse s are received regardless of the multicast table value.. mac multicast table 1 register (mtr1 offset 0x0024) the 64 bit multicast table is used for group address filtering. t he hash value is defined as the six most significant bits of the crc of the da. the two most significant bits select the register to be used, while the other determines the bit within the register. the following table shows the register bit fields. bit default r/w description 31-0 0x0 rw mtr0 multicast table 1 when appropriate bit is set, the packet received with da matches the crc hashing function is received without being filtered. note: when the receive all (rxra) or receive multicast (rxrm) bit is set in the rxcr then all multicast addresse s are received regardless of the multicast table value. interrupt enable register (inten offset 0x0028) this register enables the in terrupts from the internal or external sources. the following table shows the register bit fields. bit default r/w description 31 0 rw dmlcie dma mac link changed interrupt enable when this bit is set, the dma mac link changed interrupt is enabled. when this bit is reset, the dma mac link changed interrupt is disabled. 30 0 rw dmtie dma mac transmit interrupt enable when this bit is set, the dma mac transmit interrupt is enabled. when this bit is reset, the dma mac transmit interrupt is disabled. 29 0 rw dmrie dma mac receive interrupt enable when this bit is set, the dma mac receive interrupt is enabled. when this bit is reset, the dma mac receive interrupt is disabled. 28 0 rw dmtbuie dma mac transmit buff er unavailable interrupt enable when this bit is set, the dma mac transmit buffer unavailable interrupt is enabled. when this bit is reset, the dma mac transmit buffer unavailable interrupt is disabled. 27 0 rw dmrbuie dma mac receive buffer un available interrupt enable when this bit is set, the dma mac receive buffer unavailable interrupt is enabled. when this bit is reset, the dma mac receive buffer unavailable interrupt is disabled. 26 0 rw dmtpsie dma mac transmit pr ocess stopped interrupt enable when this bit is set, the dma mac transmit process stopped interrupt is enabled. when this bit is reset, the dma mac transmit process stopped interrupt is disabled.
micrel, inc. ksz8842-pmql/pmbl october 2007 48 m9999-100207-1. 5 bit default r/w description 25 0 rw dmrpsie dma mac receive pro cess stopped interrupt enable when this bit is set, the dma mac re ceive process stopped interrupt is enabled. when this bit is reset, the dma mac receive process stopped interrupt is disabled. 24 ? 0 ? ro reserved interrupt status register (intst offset 0x002c) this register contains the st atus bits for the cpu. when t he corresponding bit is set, the cpu is interrupted. the driver usually reads this register dur ing interrupt service routine or polling. the register bits ar e not cleared when read. each field can be masked. the following table shows the register bit fields. bit default r/w description 31 0 rw dmlcs dma mac link changed status when this bit is set, it indicates t hat the dma mac link status has changed from link up to link down or from link down to link up. this edge-triggered interrupt status is cleared by writing 1 to this bit. 30 0 rw dmts dma mac transmit status when this bit is set, it indicates t hat the dma mac has transmitted at least a frame on the dma port and the ma c is ready for new frames from the host. this edge-triggered interrupt status is cleared by writing 1 to this bit. 29 0 rw dmrs dma mac receive status when this bit is set, it indicates t hat the dma mac has received a frame from the dma port and it is ready for the host to process this edge-triggered interrupt status is cleared by writing 1 to this bit. 28 0 rw dmtbus dma mac transmit buffer unavailable status when this bit is set, it indicates that the next descriptor on the transmit list is owned by the host and cannot be acquired by the ksz8842- pmql/pmbl. the transmission process is suspended. to resume processing transmit descriptors, the host should change the ownership bit of the descriptor and then issue a transmit start command. this edge-triggered interrupt status is cleared by writing 1 to this bit. 27 0 rw dmrbus dma mac receive buffer unavailable status when this bit is set, it indicates that the descriptor list is owned by the host and cannot be acquired by the ksz8842-pmql/pmbl. the receiving process is suspended. to resume processing receive descriptors, the host should change the ownership of the descriptor and may issue a receive start command. if no receiv e start command is issued, the receiving process resumes when the next recognized incoming frame is received. after the first assertion, this bit is not asserted for any subsequent not owned receive descriptors fetches. this bit is asserted only when the previous receive descriptor was owned by the ksz8842- pmql/pmbl. this edge-triggered interrupt status is cleared by writing 1 to this bit. 26 0 rw dmtpss dma mac transmit process stopped status asserted when the dma mac transmit process enters the stopped state. this edge-triggered interrupt status is cleared by writing 1 to this bit. 25 0 rw dmrpss dma mac receive process stopped status asserted when the dma mac receive process enters t he stopped state. this edge-triggered interrupt status is cleared by writing 1 to this bit. 24 ? 0 ? ro reserved
micrel, inc. ksz8842-pmql/pmbl october 2007 49 m9999-100207-1. 5 mac additional station addr ess low register (maal0-15) the ksz8842-pmql/pmbl supports 16 additional mac addres ses for mac address filtering. this mac address is used to define one of the 16 destinat ion addresses that the ksz8842-pmql/pmbl will re spond to when receiving frames on the port. network addresses ar e generally expressed in the form of 01:23:45:67:89:ab, w here the bytes are received left to right, and the bits within each byte are rece ived right to left (lsb to msb). the actual transmitted and received bits are in the order of 10000000 11000100 10100010 11100110 10010001 11010101. the following table shows the register bit fields. bit default r/w description 31 ? 0 ? rw maal0 mac additional st ation address 0 low 4 bytes the least significant word of the additional mac 0 station address. mac additional station addr ess high register (maah0-15) the ksz8842-pmql/pmbl supports 16 additional mac addres ses for mac address filtering. this mac address is used to define one of the 16 destinat ion addresses that the ksz8842-pmql/pmbl will re spond to when receiving frames on the host port. network addresses are generally ex pressed in the form of 01:23: 45:67:89:ab, where the bytes are received left to right, and the bits within each byte are received right to left (lsb to msb). the actual transmitted and received bits are in the order of 10000000 11000100 10100010 11100110 10010001 11010101. the following table shows the register bit fields. bit default r/w description 31 0 rw maa0e mac additional station address 0 enable when set, the additional mac address is enabled for received frames. when reset, the additional mac address is disabled. 30 ? 16 0x0 ro reserved 15 - 0 ? rw maah0 mac additional stat ion address 0 high 2 bytes the most significant word of t he additional mac 0 station address. the following table shows the register map for all 16 additional mac address registers. register identifier offset add mac low 0 maal0 0x0080 add mac high 0 maah0 0x0084 add mac low 1 maal1 0x0088 add mac high 1 maah1 0x008c add mac low 2 maal2 0x0090 add mac high 2 maah2 0x0094 add mac low 3 maal3 0x0098 add mac high 3 maah3 0x009c add mac low 4 maal4 0x00a0 add mac high 4 maah4 0x00a4 add mac low 5 maal5 0x00a8 add mac high 5 maah5 0x00ac add mac low 6 maal6 0x00b0 add mac high 6 maah6 0x00b4 add mac low 7 maal7 0x00b8 add mac high 7 maah7 0x00bc add mac low 8 maal8 0x00c0 add mac high 8 maah8 0x00c4
micrel, inc. ksz8842-pmql/pmbl october 2007 50 m9999-100207-1. 5 register identifier offset add mac low 9 maal9 0x00c8 add mac high 9 maah9 0x00cc add mac low 10 maal10 0x00d0 add mac high 10 maah10 0x00d4 add mac low 11 maal11 0x00d8 add mac high 11 maah11 0x00dc add mac low 12 maal12 0x00e0 add mac high 12 maah12 0x00e4 add mac low 13 maal13 0x00e8 add mac high 13 maah13 0x00ec add mac low 14 maal14 0x00f0 add mac high 14 maah14 0x00f4 add mac low 15 maal15 0x00f8 add mac high 15 maah15 0x00fc mac/phy and control registers mac address register low (0x0200): marl this register along with the other two mac address registers are loaded starting at word location 0x10 of the eeprom upon hardware reset. the register can be modified by the software driver, but w ill not modify the original mac address value in the eeprom. the mac address is used to def ine the individual destinati on address that the ksz8842- pmql/pmbl host port will respond to when receiving unicast frames. this mac address will become the source address when sending unicast frames from the host port to port-1 or port-2. network addresses are generally expressed in the form of 01:23:45:67:89: ab, where the bytes are received from le ft to right, and the bits within each byte are received right to left (lsb to msb). the actual transmitted and received bits are in the order of 10000000 11000100 10100010 11100110 10010001 11010101. the following table shows the register bi t fields for low word of mac address. bit default r/w description 15 ? 0 ? rw marl mac address low the least significant word of the mac address mac address register middle (0x0202): marm this register along with the other two mac address registers are loaded starting at word location 0x10 of the eeprom upon hardware reset. the register can be modified by the software driver, but w ill not modify the original mac address value in the eeprom. mac address is us ed to define the individual destina tion address the ksz8842-pmql/pmbl will respond to when receiving frames. network addresses ar e generally expressed in the form of 01:23:45:67:89:ab, where the bytes are received from left to right, and the bits with in each byte are received right to left (lsb to msb). the actual transmitted and received bits are in the order of 10000000 11000100 10100010 11100110 10010001 11010101. the following table shows the register bit fields. bit default r/w description 15 ? 0 ? rw marm mac address middle the middle word of the mac address mac address register high (0x0204): marh this register along with the other two mac address registers are loaded starting at word location 0x10 of the eeprom upon hardware reset. the register can be modified by softwar e driver, but will not modify the original mac address value in the eeprom. mac address is us ed to define the individual destina tion address the ksz8842-pmql/pmbl will
micrel, inc. ksz8842-pmql/pmbl october 2007 51 m9999-100207-1. 5 respond to when receiving frames. network addresses ar e generally expressed in the form of 01:23:45:67:89:ab, where the bytes are received from left to right, and the bits with in each byte are received right to left (lsb to msb). the actual transmitted and received bits are in the order of 10000000 11000100 10100010 11100110 10010001 11010101. the following table shows the register bit fields. bit default r/w description 15-0 ? rw marh mac address high the most significant word of the mac address reserved (offset 0x0206 - 0x020a the following table shows the register bit fields. bit default r/w description 15 ? 0 0x0000 ro reserved on-chip bus control register (offset 0x0210): obcr this register controls the on-chip bus speed for the ksz 8842-pmql/pmbl. it is used for reduced power consumption when the external host cpu is running at a slow frequen cy. the default of the on-chip bus speed is 25mhz. when the external host cpu is running at a higher clock ra te, adjust the on-chip bus for the best performance. the following table shows the register bit fields. bit default r/w description 15 ? 2 ? ro reserved 1 ? 0 0x3 rw obsc on-chip bus speed control 00: 125mhz 01: 62.5mhz 10: 41.66mhz 11: 25mhz eeprom control register (offset 0x0212): eepcr ksz8842-pmql/pmbl supports de signs with and without an eeprom syst em design. to support an external eeprom, tie the eeprom enable (eeen) pin/ball to high; ot herwise, tie it to low or no connect. the ksz8842- pmql/pmbl allows software to access (read and write) the eeprom directly; that is, the eeprom access timing can be fully controlled by the software if the eeprom software access bit 4 in eepcr is set. the following table shows the register bit fields. bit default r/w description 15 ? 5 0 ro reserved 4 0 rw eesa eeprom software access 1 = enable software to access eeprom through bit 3 to bit 0. 0 = disable software to access eeprom. 3 00 ro eecb eeprom status bits bit 3: data out from eeprom. this bi t directly reflects the value of the eedi pin/ball. 2 00 rw eecb eeprom control bits bit 2: data in to eeprom. this bit directly controls the device?s the eedo pin/ball. 1 00 rw eecb eeprom control bits bit 1: serial clock. this bit directl y controls the device?s the eesk pin/ball. 0 00 rw eecb eeprom control bits bit 0: chip select. this bit directly controls the device?s the eecs pin/ball.
micrel, inc. ksz8842-pmql/pmbl october 2007 52 m9999-100207-1. 5 memory bist info register (offset 0x0214): mbir the following table shows the register bit fields. bit default r/w description 15 ? 13 0x0 ro reserved 12 ? ro txmbf tx memory bits finish when set, it indicates the memory built in self test has completed for the tx memory. 11 ? ro txmbfa tx memory bits fail when set, it indicates the memory built in self test has failed. 10 ? 5 ? ro reserved 4 ? ro rxmbf rx memory bits finish when set, it indicates the memory built in self test has completed for the rx memory. 3 ? ro rxmbfa rx memory bits fail when set, it indicates the memory built in self test has failed. 2 ? 0 ? ro reserved global reset register (offset 0x0216): grr this register holds control information programmed by the cpu to control the gl obal soft reset function. bit default r/w description 15 ? 1 0x00 ro reserved 0 0 rw global soft reset 1 = software reset active 0 = software reset inactive set two times to finish the software re set, this soft reset bit will reset pci control/status registers only. switch registers switch id and enable register (offset 0x0400): sider this register contains the switch id, and the switch-enable control. bit default r/w description 15 ? 8 0x88 ro family id chip family 7 ? 4 0x4 ro chip id 3 ? 1 000 ro revision id 0 ? rw start switch 1 = start the chip
micrel, inc. ksz8842-pmql/pmbl october 2007 53 m9999-100207-1. 5 switch global control register 1 (offset 0x0402): sgcr1 this register contains the global control for the switch function. bit default r/write description 15 0 rw pass all frames 1 = switch all packets including bad ones. used solely for debugging purposes. works in conjunction with sniffer mode only. 14 0 rw reserved. for factory test purposes only. always write 0. 13 1 rw ieee 802.3x transmit direction flow control enable 1 = will enable transmit direction flow control feature. 0 = will not enable transmit direction flow control feature. switch will not generate any flow control packets. 12 1 rw ieee 802.3x receive directi on flow control enable 1 = will enable receive direction flow control feature. 0 = will not enable receive direction flow control feature. switch will not react to any received flow control packets. 11 1 rw frame length field check 1 = will check frame length field in the ieee packets. if the actual length does not match, the packet will be dropped (for length/type field < 1500). 10 1 rw aging enable 1 = enable age function in the chip 0 = disable age function in the chip 9 0 rw fast age enable 1 = turn on fast age (800s) 8 0 rw aggressive back off enable 1 = enable more aggressive back off algorithm in half duplex mode to enhance performance. this is not an ieee standard. 6 ? 4 0x4 rw reserved 3 0x0 rw reserved 3 1 rw pass flow control packet 1 = switch will not filter 802.1x ?flow control? packets. 2 1 rw reserved 1 0 rw reserved 0 0 rw link change age 1 = link change from ?link? to ?no link? will cause fast aging (<800s) to age address table faster. after an age cycle is complete, the age logic will return to normal (300 + 75 seconds). note: if any port is unplugged, all addresses will be automatically aged out.
micrel, inc. ksz8842-pmql/pmbl october 2007 54 m9999-100207-1. 5 switch global control register 2 (offset 0x0404): sgcr2 this register contains the global control for the switch function. bit default r/w description 15 0 rw 802.1q vlan enable 1 = 802.1q vlan mode is turned on. vlan table needs to set up before the operation. 0 = 802.1q vlan is disabled. 14 0 rw igmp snoop enable 1 = igmp snoop is enabled. all the igmp packets will be forwarded to the host port. 0 = igmp snoop is disabled. 13 0 rw ipv6 mld snooping enable 1 = enable ipv6 mld snooping 12 0 rw ipv6 mld snooping option 1 = enable ipv6 mld snooping option. 11 0 rw priority scheme select 0 = always tx higher priority packets first 1 = weighted fair queuing enable. when all 4 queues has packets waiting to tx, the bandwidth allocati on is q3:q2:q1:q0 = 8:4:2:1. if any queues is empty, the highest non-empty queue will get one more weighting. for example, if q2 is em pty, q3:q2:q1:q0 will become (8+1): 0 :2 : 1. 10 ? 9 0 rw reserved. for factory test purposes only. always write 0. 8 0 rw sniff mode select 1 = will do rx and tx sniff (both source port and destination port need to match) 0 = will do rx or tx sniff (either source port or destination port needs to match). this is the mode used to implement rx only sniff. 7 1 rw unicast port-vlan mismatch discard 1 = all packets can not cross vlan boundary 0 = unicast packets (excluding unknown/multicast/broadcast) can cross vlan boundary 6 1 rw multicast storm protection disable 1 = ?broadcast storm protection? does not include multicast packets. only da = ffffffffffff packets will be regulated. 0 = ?broadcast storm protection? includes da = ffffffffffff and da[40] = 1 packets. 5 1 rw back pressure mode 1 = carrier sense based backpressure is selected 0 = collision based backpressure is selected 4 1 rw flow control and back pressure fair mode 1 = fair mode is selected. in this mode, if a flow control port and a non- flow control port talk to the same destination port, packets from the non- flow control port may be dropped. this is to prevent the flow control port from being flow controlled for an extended period of time. 0 = in this mode, if a flow control port and a non-flow control port talk to the same destination port, the flow control port will be flow controlled. this may not be ?fair? to the flow control port.
micrel, inc. ksz8842-pmql/pmbl october 2007 55 m9999-100207-1. 5 bit default r/w description 3 0 rw no excessive collision drop 1 = the switch will not drop packets when 16 or more collisions occur. 0 = the switch will drop packets when 16 or more collisions occur. 2 0 rw huge packet support 1 = will accept packet sizes up to 1916 bytes (inclusive). this bit setting will override setting from bit 1 of the same register. 0 = the max packet size will be det ermined by bit 1 of this register. 1 0 rw legal maximum packet size check enable 0 = will accept packet sizes up to 1536 bytes (inclusive). 1 = 1522 bytes for tagged packets, 1518 bytes for untagged packets. any packets larger than the specified value will be dropped. 0 1 rw priority buffer reserve 1 = each ports pre-allocated 48 buffers, used exclusively for high priority packets(q3,q2,q1). effective only when multiple queues feature is turned on. 0 = each ports pre-allocated 48 buffers, used for all priority packets (q3,q2,q1,q0). switch global control register 3 (offset 0x0406): sgcr3 this register contains the global control for the switch function. bit default r/w description 15 ? 8 0x63 rw broadcast storm protection rate bit [7:0] these bits, along with sgcr3[2:0], determines how many ?64-byte blocks? of packet data are allowed on an input port in a pr eset period. the period is 67ms for 100base-t or 670ms for 10base-t. the default is 1%. 7 0 rw repeater mode 1 = enable repeater mode 0 = normal mode note: the repeater only supports 100base-t, halfduplex modes. when set to repeater mode, need to disable fo llow control in register mdtxc[9] 6 0 rw switch host port duplex mode 1 = enable switch host interface half duplex mode. 0 = enable switch host interface full duplex mode. (keep default value to match dma mac to the full duplex mode only). 5 0 rw switch host port flow control enable 1 = enable full duplex flow control on switch host interface. 0 = disable full duplex flow control on switch host interface. 4 0 rw reserved (must be 0) 3 0 rw null vid replacement 1 = replaces null vid with port vid(12 bits) 0 = no replacement for null vid 2 ? 0 000 rw broadcast storm protection rate bit [10:8] these bits, along with sgcr3[15-8], determines how many ?64-byte blocks? of packet data allowed on an input port in a preset period. the period is 67ms for 100base-t or 670ms for 10base-t. the default is 1%. rate: 148,800 frames/sec * 67 ms/interval * 1% = 99 frames/interval (approx.) = 0x63
micrel, inc. ksz8842-pmql/pmbl october 2007 56 m9999-100207-1. 5 switch global control register 4 (offset 0x0408): sgcr4 this register contains the global control for the switch function. bit default r/w description 15 ? 0 0x2400 rw reserved. for factory testing purposes only. switch global control register 5 (offset 0x040a): sgcr5 this register contains the global control for the switch function. bit default r/w description 15 0 rw ledsel1 see description for bit 9. 14 0 rw reserved 13 0 rw reserved 12 0 rw testing mode reserved , must be 0 11 ? 10 0 rw reserved 9 0 rw ledsel0 the two register bits ledsel1 and leds el0, are used to select the led mode. port x led indicators as switch mode defined as below: [ledsel1, ledsel0] [0, 0] [0, 1] pxled3 ? ? pxled2 link/act 100link/act pxled1 full_dpx/col 10link/act pxled0 speed full_dpx [ledsel1, ledsel0] [1, 0] [1, 1] pxled3 act ? pxled2 link ? pxled1 full_dpx/col ? pxled0 speed ? port 1 and port 2 led indicators as repeater mode defined as follows: switch global control register 5: sgcr5 bit [15,9] [0,0] default [0,1] [1,0] [1,1] p1led3 rpt_col ? p1led2 rpt_link3/rx ? p1led1 rpt_link2/rx ? p1led0 rpt_link1/rx ?
micrel, inc. ksz8842-pmql/pmbl october 2007 57 m9999-100207-1. 5 bit default r/w description switch global control register 5: sgcr5 bit [15,9] [0,0] default [0,1] [1,0] [1,1] p2led3 rpt_act ? p2led2 rpt_err3 ? p2led1 rpt_err2 ? p2led0 rpt_err1 ? note: see pin/ball description for detail definition 8 0 rw reserved 7 ? 0 0x24 rw reserved. for factory testing purposes only. switch global control register 6 (offset 0x0410): sgcr6 this register contains the global control for the switch function. bit default r/w description 15:14 0x3 rw tag_0x7 ieee 802.1p mapping. the value in this field is used as the frame?s priority when its ieee tag has a value of 0x7. 13:12 0x3 rw tag_0x6 ieee 802.1p mapping. the value in this field is used as the frame?s priority when its ieee tag has a value of 0x6. 11:10 0x2 rw tag_0x5 ieee 802.1p mapping. the value in this field is used as the frame?s priority when its ieee tag has a value of 0x5. 9:8 0x2 rw tag_0x4 ieee 802.1p mapping. the value in this field is used as the frame?s priority when its ieee tag has a value of 0x4. 7:6 0x1 rw tag_0x3 ieee 802.1p mapping. the value in this field is used as the frame?s priority when its ieee tag has a value of 0x3. 5:4 0x1 rw tag_0x2 ieee 802.1p mapping. the value in this field is used as the frame?s priority when its ieee tag has a value of 0x2. 3:2 0x0 rw tag_0x1 ieee 802.1p mapping. the value in this field is used as the frame?s priority when its ieee tag has a value of 0x1. 1:0 0x0 rw tag_0x0 ieee 802.1p mapping. the value in this field is used as the frame?s priority when its ieee tag has a value of 0x0.
micrel, inc. ksz8842-pmql/pmbl october 2007 58 m9999-100207-1. 5 switch global control register 7 (0x0412): sgcr7 this register contains the global control for the switch function. bit default r/w description 15 ? 8 0 rw 7 0 rw unknown default port enable send packets with unknown destination address to specified ports in bits [2:0]. 1 = enable to send unknown da packet 6 ? 3 0x0 rw for factory test only. always write 0. 2 ? 0 0x7 rw unknown packet default port(s) specify which ports to send packets wi th unknown destination addresses. feature is enabled by bit [7]. bit 2: for the host port bit 1: for the port 2 bit 0: for the port 1 reserved (offset 0x0414 - 0x046f) mac address register 1 (offset 0x0470): macar1 this register contains the mac address for the switch function. this mac ad dress is used to send the pause frame. bit default r/w description 15 ? 0 0x0010 rw maca[47:32] specify host mac address 1. this value must be the same as mac address register high (0x0204): marh. mac address register 2 (offset 0x0472): macar2 this register contains the mac address for the switch function. this mac ad dress is used to send the pause frame. bit default r/w description 15 ? 0 0xa1ff rw maca[31:16] specify host mac address 2. this value must be the same as mac address register middle (0x0202): marm. mac address register 3 (offset 0x0474): macar3 this register contains the mac address for the switch function. this mac ad dress is used to send the pause frame. bit default r/w description 15 ? 0 0xffff rw maca[15:0] specify host mac address 3. this value must be the same as mac address register low (0x0200): marl. reserved (offset 0x0476 - 0x047f) this register is reserved. bit default r/w description 15 ? 0 0x0000 ro reserved
micrel, inc. ksz8842-pmql/pmbl october 2007 59 m9999-100207-1. 5 priority control register 1 (offset 0x0480): tosr1 this register contains the tos priori ty control for the switch function. the ipv4/ipv6 tos priority control regi sters implement a fully decoded 64 dscp (differentiated services code point) register used to determine priority from the 6 bit tos field in the ip header. the most significant 6 bits of the tos field are fully decoded into 64 possibilities, and the singular code that results is com pared against the co rresponding bits in the dscp register to determine the priority. bit default r/w description 15:14 0 rw dscp[15:14] the value in this field is used as the frame?s priority when bits [7:2] of it ip tos/diffserv/traffic cl ass value is 0x1c. 13:12 0 rw dscp[13:12] the value in this field is used as the frame?s priority when bits [7:2] of it ip tos/diffserv/traffic cl ass value is 0x18. 11:10 0 rw dscp[11:10] the value in this field is used as the frame?s priority when bits [7:2] of it ip tos/diffserv/traffic cl ass value is 0x14. 9:8 0 rw dscp[9:8] the value in this field is used as the frame?s priority when bits [7:2] of it ip tos/diffserv/traffic cl ass value is 0x10. 7:6 0 rw dscp[7:6] the value in this field is used as the frame?s priority when bits [7:2] of it ip tos/diffserv/traffic cl ass value is 0x0c. 5:4 0 rw dscp[5:4] the value in this field is used as the frame?s priority when bits [7:2] of it ip tos/diffserv/traffic cl ass value is 0x08. 3:2 0 rw dscp[3:2] the value in this field is used as the frame?s priority when bits [7:2] of it ip tos/diffserv/traffic cl ass value is 0x04. 1:0 0 rw dscp[1:0] the value in this field is used as the frame?s priority when bits [7:2] of it ip tos/diffserv/traffic cl ass value is 0x00. tos priority control register 2 (offset 0x482): tosr2 this register contains the tos priori ty control for the switch function. bit default r/w description 15:14 0 rw dscp[31:30] the value in this field is used as the frame?s priority when bits [7:2] of it ip tos/diffserv/traffic cl ass value is 0x3c. 13:12 0 rw dscp[29:28] the value in this field is used as the frame?s priority when bits [7:2] of it ip tos/diffserv/traffic cl ass value is 0x38. 11:10 0 rw dscp[27:26] the value in this field is used as the frame?s priority when bits [7:2] of it ip tos/diffserv/traffic cl ass value is 0x34. 9:8 0 rw dscp[25:24] the value in this field is used as the frame?s priority when bits [7:2] of it ip tos/diffserv/traffic cl ass value is 0x30. 7:6 0 rw dscp[23:22] the value in this field is used as the frame?s priority when bits [7:2] of it ip tos/diffserv/traffic cl ass value is 0x2c.
micrel, inc. ksz8842-pmql/pmbl october 2007 60 m9999-100207-1. 5 bit default r/w description 5:4 0 rw dscp[21:20] the value in this field is used as the frame?s priority when bits [7:2] of it ip tos/diffserv/traffic cl ass value is 0x28. 3:2 0 rw dscp[19:18] the value in this field is used as the frame?s priority when bits [7:2] of it ip tos/diffserv/traffic cl ass value is 0x24. 1:0 0 rw dscp[17:16] the value in this field is used as the frame?s priority when bits [7:2] of it ip tos/diffserv/traffic cl ass value is 0x20. tos priority control register 3 (offset 0x484): tosr3 this register contains the tos priori ty control for the switch function. bit default r/w description 15:14 0 rw dscp[47:46] the value in this field is used as the frame?s priority when bits [7:2] of it ip tos/diffserv/traffic cl ass value is 0x5c. 13:12 0 rw dscp[45:44] the value in this field is used as the frame?s priority when bits [7:2] of it ip tos/diffserv/traffic cl ass value is 0x58. 11:10 0 rw dscp[43:42] the value in this field is used as the frame?s priority when bits [7:2] of it ip tos/diffserv/traffic cl ass value is 0x54. 9:8 0 rw dscp[41:40] the value in this field is used as the frame?s priority when bits [7:2] of it ip tos/diffserv/traffic cl ass value is 0x50. 7:6 0 rw dscp[39:38] the value in this field is used as the frame?s priority when bits [7:2] of it ip tos/diffserv/traffic cl ass value is 0x4c. 5:4 0 rw dscp[37:36] the value in this field is used as the frame?s priority when bits [7:2] of it ip tos/diffserv/traffic cl ass value is 0x48. 3:2 0 rw dscp[35:34] the value in this field is used as the frame?s priority when bits [7:2] of it ip tos/diffserv/traffic cl ass value is 0x44. 1:0 0 rw dscp[33:32] the value in this field is used as the frame?s priority when bits [7:2] of it ip tos/diffserv/traffic cl ass value is 0x40. tos priority control register 4 (offset 0x486): tosr4 this register contains the tos priori ty control for the switch function. bit default r/w description 15:14 0 rw dscp[63:62] the value in this field is used as the frame?s priority when bits [7:2] of it ip tos/diffserv/traffic cl ass value is 0x7c. 13:12 0 rw dscp[61:60] the value in this field is used as the frame?s priority when bits [7:2] of it ip tos/diffserv/traffic cl ass value is 0x78.
micrel, inc. ksz8842-pmql/pmbl october 2007 61 m9999-100207-1. 5 bit default r/w description 11:10 0 rw dscp[59:58] the value in this field is used as the frame?s priority when bits [7:2] of it ip tos/diffserv/traffic cl ass value is 0x74. 9:8 0 rw dscp[57:56] the value in this field is used as the frame?s priority when bits [7:2] of it ip tos/diffserv/traffic cl ass value is 0x70. 7:6 0 rw dscp[55:54] the value in this field is used as the frame?s priority when bits [7:2] of it ip tos/diffserv/traffic cl ass value is 0x6c. 5:4 0 rw dscp[53:52] the value in this field is used as the frame?s priority when bits [7:2] of it ip tos/diffserv/traffic cl ass value is 0x68. 3:2 0 rw dscp[51:50] the value in this field is used as the frame?s priority when bits [7:2] of it ip tos/diffserv/traffic cl ass value is 0x64. 1:0 0 rw dscp[49:48] the value in this field is used as the frame?s priority when bits [7:2] of it ip tos/diffserv/traffic cl ass value is 0x60. tos priority control register 5 (offset 0x488): tosr5 this register contains the tos priori ty control for the switch function. bit default r/w description 15:14 0 rw dscp[79:78] the value in this field is used as the frame?s priority when bits [7:2] of it ip tos/diffserv/traffic cl ass value is 0x9c. 13:12 0 rw dscp[77:76] the value in this field is used as the frame?s priority when bits [7:2] of it ip tos/diffserv/traffic cl ass value is 0x98. 11:10 0 rw dscp[75:74] the value in this field is used as the frame?s priority when bits [7:2] of it ip tos/diffserv/traffic cl ass value is 0x94. 9:8 0 rw dscp[73:72] the value in this field is used as the frame?s priority when bits [7:2] of it ip tos/diffserv/traffic cl ass value is 0x90. 7:6 0 rw dscp[71:70] the value in this field is used as the frame?s priority when bits [7:2] of it ip tos/diffserv/traffic cl ass value is 0x8c. 5:4 0 rw dscp[69:68] the value in this field is used as the frame?s priority when bits [7:2] of it ip tos/diffserv/traffic cl ass value is 0x88. 3:2 0 rw dscp[67:66] the value in this field is used as the frame?s priority when bits [7:2] of it ip tos/diffserv/traffic cl ass value is 0x84. 1:0 0 rw dscp[65:64] the value in this field is used as the frame?s priority when bits [7:2] of it ip tos/diffserv/traffic cl ass value is 0x80.
micrel, inc. ksz8842-pmql/pmbl october 2007 62 m9999-100207-1. 5 tos priority control register 6 (offset 0x48a): tosr6 this register contains the tos priori ty control for the switch function. bit default r/w description 15:14 0 rw dscp[95:94] the value in this field is used as the frame?s priority when bits [7:2] of it ip tos/diffserv/traffic cl ass value is 0xbc. 13:12 0 rw dscp[93:92] the value in this field is used as the frame?s priority when bits [7:2] of it ip tos/diffserv/traffic cl ass value is 0xb8. 11:10 0 rw dscp[91:90] the value in this field is used as the frame?s priority when bits [7:2] of it ip tos/diffserv/traffic cl ass value is 0xb4. 9:8 0 rw dscp[89:88] the value in this field is used as the frame?s priority when bits [7:2] of it ip tos/diffserv/traffic cl ass value is 0xb0. 7:6 0 rw dscp[87:86] the value in this field is used as the frame?s priority when bits [7:2] of it ip tos/diffserv/traffic cl ass value is 0xac. 5:4 0 rw dscp[85:84] the value in this field is used as the frame?s priority when bits [7:2] of it ip tos/diffserv/traffic cl ass value is 0xa8. 3:2 0 rw dscp[83:82] the value in this field is used as the frame?s priority when bits [7:2] of it ip tos/diffserv/traffic cl ass value is 0xa4. 1:0 0 rw dscp[81:80] the value in this field is used as the frame?s priority when bits [7:2] of it ip tos/diffserv/traffic cl ass value is 0xa0. tos priority control register 7 (offset 0x490): tosr7 this register contains the tos priori ty control for the switch function. bit default r/w description 15:14 0 rw dscp[111:110] the value in this field is used as the frame?s priority when bits [7:2] of it ip tos/diffserv/traffic cl ass value is 0xdc. 13:12 0 rw dscp[109:108] the value in this field is used as the frame?s priority when bits [7:2] of it ip tos/diffserv/traffic cl ass value is 0xd8. 11:10 0 rw dscp[107:106] the value in this field is used as the frame?s priority when bits [7:2] of it ip tos/diffserv/traffic cl ass value is 0xd4. 9:8 0 rw dscp[105:104] the value in this field is used as the frame?s priority when bits [7:2] of it ip tos/diffserv/traffic cl ass value is 0xd0. 7:6 0 rw dscp[103:102] the value in this field is used as the frame?s priority when bits [7:2] of it ip tos/diffserv/traffic class value is 0xcc. 5:4 0 rw dscp[101:100] the value in this field is used as the frame?s priority when bits [7:2] of it ip tos/diffserv/traffic cl ass value is 0xc8.
micrel, inc. ksz8842-pmql/pmbl october 2007 63 m9999-100207-1. 5 bit default r/w description 3:2 0 rw dscp[99:98] the value in this field is used as the frame?s priority when bits [7:2] of it ip tos/diffserv/traffic cl ass value is 0xc4. 1:0 0 rw dscp[97:96] the value in this field is used as the frame?s priority when bits [7:2] of it ip tos/diffserv/traffic cl ass value is 0xc0. tos priority control register 8 (offset 0x492): tosr8 this register contains the tos priori ty control for the switch function. bit default r/w description 15:14 0 rw dscp[127:126] the value in this field is used as the frame?s priority when bits [7:2] of it ip tos/diffserv/traffic cl ass value is 0xfc. 13:12 0 rw dscp[125:124] the value in this field is used as the frame?s priority when bits [7:2] of it ip tos/diffserv/traffic cl ass value is 0xf8. 11:10 0 rw dscp[123:122] the value in this field is used as the frame?s priority when bits [7:2] of it ip tos/diffserv/traffic cl ass value is 0xf4. 9:8 0 rw dscp[121:120] the value in this field is used as the frame?s priority when bits [7:2] of it ip tos/diffserv/traffic cl ass value is 0xf0. 7:6 0 rw dscp[119:118] the value in this field is used as the frame?s priority when bits [7:2] of it ip tos/diffserv/traffic cl ass value is 0xec. 5:4 0 rw dscp[117:116] the value in this field is used as the frame?s priority when bits [7:2] of it ip tos/diffserv/traffic cl ass value is 0xe8. 3:2 0 rw dscp[115:114] the value in this field is used as the frame?s priority when bits [7:2] of it ip tos/diffserv/traffic cl ass value is 0xe4. 1:0 0 rw dscp[113:112] the value in this field is used as the frame?s priority when bits [7:2] of it ip tos/diffserv/traffic cl ass value is 0xe0. reserved (offset 0x0494 - 0x049a) this register is reserved. bit default r/w description 15 ? 0 0x0000 ro reserved
micrel, inc. ksz8842-pmql/pmbl october 2007 64 m9999-100207-1. 5 indirect access control register (offset 0x04a0): iacr this register contains the indirect control for the switch function. bit default r/w description 15 ? 13 000 rw reserved 12 0 rw read high. write low 1 = read cycle 0 = write cycle 11:10 00 rw table select 00 = static mac address table selected 01 = vlan table selected 10 = dynamic address table selected 11 = mib counter selected 9 ? 0 0x000 rw indirect address bit 9-0 of indirect address note: (1) write iacr will actually trigger a command. read or write access is determined by register bit 12. indirect access data register 1 (offset 0x04a2): iadr1 this register contains the indire ct data for the switch function. bit default r/w description 15 ? 8 0x000 ro reserved 7 0 ro cpu read status only for dynamic and statistics counter reads. 1 = read is still in progress 0 = read has completed 6 ? 3 0x0 ro reserved 2 ? 0 000 ro indirect data. bit 66-64 of indirect data indirect access data register 2 (offset 0x04a4): iadr2 this register contains the indire ct data for the switch function. bit default r/w description 15 ? 0 0x0000 rw indirect data bit 47-32 of indirect data indirect access data register 3 (offset 0x04a6): iadr3 this register contains the indire ct data for the switch function. bit default r/w description 15 ? 0 0x0000 rw indirect data bit 63-48 of indirect data indirect access data register 4 (offset 0x04a8): iadr4 this register contains the indire ct data for the switch function. bit default r/w description 15 ? 0 0x0000 rw indirect data bit 15-0 of indirect data
micrel, inc. ksz8842-pmql/pmbl october 2007 65 m9999-100207-1. 5 indirect access data register 5 (offset 0x04aa): iadr5 this register contains the indire ct data for the switch function. bit default r/w description 15 ? 0 0x0000 rw indirect data bit 31-16 of indirect data reserved (offset 0x04b0 - 0x04ba) reserved (offset 0x04c0 ?0x04cf) phy 1 mii basic control register (offset 0x04d0): p1mbcr this register contains the mii cont rol for the switch port 1 function. bit default r/w description is the same as: 15 0 ro soft reset not supported 14 0 rw loop back 1 = perform loop back as follows: start: rxp1/rxm1 (port 2) loop back: pmd/pma of port 1?s phy end: txp1/txm1 (port 2) 0 = normal operation. p1cr4, bit 8 13 0 rw force 100 1 = 100 mbps if an is disabled (bit 12) 0 = 10 mbps if an is disabled (bit 12) p1cr4, bit 6 12 1 rw an enable 1 = auto-negotiation enabled 0 = auto-negotiation disabled p1cr4, bit 7 11 0 rw power down 1 = power down the phy 1 0 = normal operation p1cr4, bit 11 10 0 ro isolate not supported 9 0 rw restart an 1 = restart auto-negotiation 0 = normal operation p1cr4, bit 13 8 0 rw force full duplex 1 = full duplex if an is disabled (bit 12) 0 = half duplex if an is disabled (bit 12) p1cr4, bit 5 7 0 ro collision test not supported 6 0 ro reserved 5 0 r/w hp_mdix 1 = hp auto mdix mode 0 = micrel auto mdix mode p1sr, bit 15 4 0 rw force mdix 1 = force mdix 0 = normal operation p1cr4, bit 9
micrel, inc. ksz8842-pmql/pmbl october 2007 66 m9999-100207-1. 5 bit default r/w description is the same as: 3 0 rw disable mdix 1 = disable auto mdix 0 = normal operation p1cr4, bit 10 2 0 rw disable far end fault 1 = disable far end fault detection 0 = normal operation p1cr4, bit 12 1 0 rw disable transmit 1 = disable transmit 0 = normal operation p1cr4, bit 14 0 0 rw disable led 1 = disable led 0 = normal operation p1cr4, bit 15 phy 1 mii basic status register (offset 0x04d2): p1mbsr this register contains the mii cont rol for the switch port 1 function. bit default r/w description is the same as: 15 0 ro t4 capable 1 = 100 baset4 capable 0 = not 100 baset4 capable 14 1 ro 100 full capable 1 = 100basetx full duplex capable 0 = not capable of 100basetx full duplex always 1 13 1 ro 100 half capable 1 = 100basetx half duplex capable 0 = not 100basetx half duplex capable always 1 12 1 ro 10 full capable 1 = 10baset full duplex capable 0 = not 10baset full duplex capable always 1 11 1 ro 10 half capable 1 = 10baset half duplex capable 0 = not 10baset half duplex capable always 1 10 ? 7 0 ro reserved 6 0 ro preamble suppressed not supported 5 0 ro an complete 1 = auto-negotiation complete 0 = auto-negotiation not completed p1sr, bit 6 4 0 ro far end fault 1 = far end fault detected 0 = no far end fault detected p1sr, bit 8 3 1 ro an capable 1 = auto-negotiation capable 0 = not auto-negotiation capable p1cr4, bit 7 2 0 ro link status 1 = link is up 0 = link is down p1sr, bit 5
micrel, inc. ksz8842-pmql/pmbl october 2007 67 m9999-100207-1. 5 bit default r/w description is the same as: 1 0 ro jabber test not supported 0 0 ro extended capable 1 = extended register capable 0 = not extended register capable phy 1 phyid low register (offset 0x04d4): phy1ilr this register contains the phy id (low) for the switch port 1 function. bit default r/w description 15 ? 0 0x1430 ro phyid low low order phyid bits phy 1 phyid high register (offset 0x04d6): phy1ihr this register contains the phy id (h igh) for the switch port 1 function. bit default r/w description 15 ? 0 0x0022 ro phyid high high order phyid bits phy 1 auto-negotiation advertisemen t register (offset 0x04d8): p1anar this register contains the auto-negotiation adv ertisement for the switch port 1 function. bit default r/w description is the same as: 15 0 ro next page not supported 14 0 ro reserved 13 0 ro remote fault not supported 12:11 0 ro reserved 10 1 rw pause (follow control capability) 1 = advertise pause ability 0 = do not advertise pause ability p1cr4, bit 4 9 0 rw reserved 8 1 rw adv 100 full 1 = advertise 100 full duplex ability 0 = do not advertise 100 full duplex ability p1cr4, bit 3 7 1 rw adv 100 half 1 = advertise 100 half duplex ability 0 = do not advertise 100 half duplex ability p1cr4, bit 2 6 1 rw adv 10 full 1 = advertise 10 full duplex ability 0 = do not advertise 10 full duplex ability p1cr4, bit 1 5 1 rw adv 10 half 1 = advertise 10 half duplex ability 0 = do not advertise 10 half duplex ability p1cr4, bit 0 4 ? 0 0_0001 ro selector field 802.3
micrel, inc. ksz8842-pmql/pmbl october 2007 68 m9999-100207-1. 5 phy 1 auto-negotiation link partner ab ility register (offset 0x04da): p1anlpr this register contains the aut o-negotiation link partner ability fo r the switch port 1 function. bit default r/w description is the same as: 15 0 ro next page not supported 14 0 ro lp ack not supported 13 0 ro remote fault not supported 12:11 0 ro reserved 10 0 ro pause link partner pause capability p1sr, bit 4 9 0 ro reserved 8 0 ro adv 100 full link partner 100 full capability p1sr, bit 3 7 0 ro adv 100 half link partner 100 half capability p1sr, bit 2 6 0 ro adv 10 full link partner 10 full capability p1sr, bit 1 5 0 ro adv 10 half link partner 10 half capability p1sr, bit 0 4 ? 0 0_0000 ro reserved phy 2 mii basic control register (offset 0x04e0): p2mbcr this register contains the mii cont rol for the switch port 2 function. bit default r/w description is the same as: 15 0 ro soft reset not supported 14 0 rw loop back 1 = perform loop back, as indicated: start: rxp2/rxm2 (port 1) loop back: pmd/pma of port 2?s phy end: txp2/txm2 (port 1) 0 = normal operation. p2cr4, bit 8 13 0 rw force 100 1 = 100 mbps if an is disabled (bit 12) 0 = 10 mbps if an is disabled (bit 12) p2cr4, bit 6 12 1 rw an enable 1 = auto-negotiation enabled 0 = auto-negotiation disabled 11 0 rw power down 1 = power down the phy 2 0 = normal operation p2cr4, bit 11 10 0 ro isolate not supported
micrel, inc. ksz8842-pmql/pmbl october 2007 69 m9999-100207-1. 5 bit default r/w description is the same as: 9 0 rw restart an 1 = restart auto-negotiation 0 = normal operation p2cr4, bit 13 8 0 rw force full duplex 1 = full duplex if an is disabled (bit 12) 0 = half duplex if an is disabled (bit 12) p2cr4, bit 5 7 0 ro collision test not supported 6 0 ro reserved 5 0 r/w hp_mdix 1 = hp auto mdix mode 0 = micrel auto mdix mode p2sr, bit 15 4 0 rw force mdix 1 = force mdix 0 = normal operation p2cr4, bit 9 3 0 rw disable mdix 1 = disable auto mdix 0 = normal operation p2cr4, bit 10 2 0 rw disable far end fault 1 = disable far end fault detection 0 = normal operation p2cr4, bit 12 1 0 rw disable transmit 1 = disable transmit 0 = normal operation p2cr4, bit 14 0 0 rw disable led 1 = disable led 0 = normal operation p2cr4, bit 15 phy 2 mii basic status register (offset 0x04e2): p2mbsr this register contains the mii cont rol for the switch port 2 function. bit default r/w description is the same as: 15 0 ro t4 capable 1 = 100 baset4 capable 0 = not 100 baset4 capable 14 1 ro 100 full capable 1 = 100basetx full duplex capable 0 = not capable of 100basetx full duplex always 1 13 1 ro 100 half capable 1 = 100basetx half duplex capable 0 = not 100basetx half duplex capable always 1 12 1 ro 10 full capable 1 = 10baset full duplex capable 0 = not 10baset full duplex capable always 1 11 1 ro 10 half capable 1 = 10baset half duplex capable 0 = not 10baset half duplex capable always 1
micrel, inc. ksz8842-pmql/pmbl october 2007 70 m9999-100207-1. 5 bit default r/w description is the same as: 10-7 0 ro reserved 6 0 ro preamble suppressed not supported 5 0 ro an complete 1 = auto-negotiation complete 0 = auto-negotiation not completed p2sr, bit 6 4 0 ro far end fault 1 = far end fault detected 0 = no far end fault detected p2sr, bit 8 3 1 ro an capable 1 = auto-negotiation capable 0 = not auto-negotiation capable p2cr4, bit 7 2 0 ro link status 1 = link is up 0 = link is down p2sr, bit 5 1 0 ro jabber test not supported 0 0 ro extended capable 1 = extended register capable 0 = not extended register capable phy 2 phyid low register (offset 0x04e4): phy2ilr this register contains the phy id (low) for the switch port 2 function. bit default r/w description 15 ? 0 0x1430 ro phyid low low order phyid bits phy 2 phyid high register (offset 0x04e6): phy2ihr this register contains the phy id (h igh) for the switch port 2 function. bit default r/w description 15 ? 0 0x0022 ro phyid high high order phyid bits phy 2 auto-negotiation advertisemen t register (offset 0x04e8): p2anar this register contains the auto-negotiation adv ertisement for the switch port 2 function. bit default r/w description is the same as: 15 0 ro next page not supported 14 0 ro reserved 13 0 ro remote fault not supported 12:11 0 ro reserved 10 1 rw pause 1 = advertise pause ability 0 = do not advertise pause ability p2cr4, bit 4 9 0 rw reserved
micrel, inc. ksz8842-pmql/pmbl october 2007 71 m9999-100207-1. 5 bit default r/w description is the same as: 8 1 rw adv 100 full 1 = advertise 100 full duplex ability 0 = do not advertise 100 full duplex ability p2cr4, bit 3 7 1 rw adv 100 half 1 = advertise 100 half duplex ability 0 = do not advertise 100 half duplex ability p2cr4, bit 2 6 1 rw adv 10 full 1 = advertise 10 full duplex ability 0 = do not advertise 10 full duplex ability p2cr4, bit 1 5 1 rw adv 10 half 1 = advertise 10 half duplex ability 0 = do not advertise 10 half duplex ability p2cr4, bit 0 4 ? 0 00001 ro selector field 802.3 phy 2 auto-negotiation link partner ab ility register (offse t 0x04ea): p2anlpr this register contains the aut o-negotiation link partner ability fo r the switch port 2 function. bit default r/w description is the same as: 15 0 ro next page not supported 14 0 ro lp ack not supported 13 0 ro remote fault not supported 12:11 0 ro reserved 10 0 ro pause link partner pause capability p2sr, bit 4 9 0 ro reserved 8 0 ro adv 100 full link partner 100 full capability p2sr, bit 3 7 0 ro adv 100 half link partner 100 half capability p2sr, bit 2 6 0 ro adv 10 full link partner 10 full capability p2sr, bit 1 5 0 ro adv 10 half link partner 10 half capability p2sr, bit 0 4 ? 0 0_0000 ro reserved
micrel, inc. ksz8842-pmql/pmbl october 2007 72 m9999-100207-1. 5 phy1 linkmd control/status (offset 0x04f0): p1vct this register contains the link md control and status of phy 1: bit default r/w description is the same as: 15 0 (self_clear) rw vct_enable 1 = the cable diagnostic test is enabled. it?ll be self- cleared after vct test is done 0 = it indicates the cable diagnostic test is completed and the status information is valid for read p1scslmd, bit 12 14:13 0 ro vct_result [00] = normal condition [01] = open condition has been detected in cable [10] = short condition has been detected in cable [11] = cable diagnostic test is failed p1scslmd, bits 14-13 12 - ro vct 10m short 1 = less than 10 meter short p1scslmd, bit 15 11 ? 9 0 ro reserved 8 ? 0 0 ro vct_fault_count distance to the fault. the distance is approximately 0.4m x vct_fault_count p1scslmd, bits 8- 0 phy1 special control/status regi ster (offset 0x04f2): p1phyctrl this register contains the contro l and status information of phy1: bit default r/w description is the same as: 15 ? 6 0 ro reserved 5 0 ro polarity reverse (polrvs) 1 = polarity is reversed 0 = polarity is not reversed p1sr, bit 13 4 0 ro mdix status (mdix_st) 1 = mdi 0 = mdix p1sr, bit 7 3 0 rw force link (force_lnk) 1 = force link pass 0 = normal operation p1scslmd, bit 11 2 1 rw power saving (pwrsave) 1 = disable 0 = enable power saving p1scslmd, bit 10 1 0 rw remote loop back (near end loop back ) 1 = loop back at pmd/pma of port 1?s phy 0 = normal operation. p1scslmd, bit 9 0 0 rw reserved
micrel, inc. ksz8842-pmql/pmbl october 2007 73 m9999-100207-1. 5 phy2 linkmd control/status (offset 0x04f4): p2vct this register contains the link md control and status of phy 2: bit default r/w description is the same as: 15 0 (self_clear) rw vct_enable 1 = the cable diagnostic test is enabled. it?ll be self- cleared after vct test is done 0 = it indicates the cable diagnostic test is completed and the status information is valid for read p2scslmd, bit 12 14:13 0 ro vct_result [00] = normal condition [01] = open condition has been detected in cable [10] = short condition has been detected in cable [11] = cable diagnostic test is failed p2scslmd, bits 14-13 12 ? ro vct 10m short 1 = less than 10 meter short p2scslmd, bit 15 11 ? 9 0 ro reserved 8 ? 0 0 ro vct_fault_count distance to the fault. the distance is approximately 0.4m x vct_fault_count p2scslmd, bits 8- 0 phy2 special control/status regist er (offset 0x04f6): p2phyctrl this register contains the contro l and status information of phy2: bit default r/w description is the same as: 15 ? 6 0 ro reserved 5 0 ro polarity reverse (polrvs) 1 = polarity is reversed 0 = polarity is not reversed p2sr, bit 13 4 0 ro mdix status (mdix_st) 1 = mdi 0 = mdix p2sr, bit 7 3 0 rw force link (force_lnk) 1 = force link pass 0 = normal operation p2scslmd, bit 11 2 1 rw power saving (pwrsave) 1 = disable 0 = enable power saving p2scslmd, bit 10 1 0 rw remote loop back (near end loop back ) 1 = loop back at pmd/pma of port 2?s phy 0 = normal operation. p2scslmd, bit 9 0 0 rw reserved reserved (offset 0x04f8 - 0x04fa) bit default r/w description 15 ? 0 0x0000 ro reserved
micrel, inc. ksz8842-pmql/pmbl october 2007 74 m9999-100207-1. 5 port 1 control register 1 (offset 0x0500): p1cr1 this register contains the global per port control for the switch port 1 function. bit default r/w description 15 ? 8 0x00 ro reserved 7 0 rw broadcast storm protection enable 1 = enable broadcast storm protecti on for ingress packets on the port 0 = disable broadcast storm protection 6 0 rw diffserv priority classification enable 1 = enable diffserv priority classification for ingress packets on port 0 = disable diffserv function 5 0 rw 802.1p priority classification enable 1 = enable 802.1p priority classification for ingress packets on port 0 = disable 802.1p 4:3 0 rw port based priority classification 00 = ingress packets on port 1 will be classified as priority 0 queue if ?diffserv? or ?802.1p? classification is not enabled or fails to classify. 01 = ingress packets on port 1 will be classified as priority 1 queue if ?diffserv? or ?802.1p? classification is not enabled or fails to classify. 10 = ingress packets on port 1 will be classified as priority 2 queue if ?diffserv? or ?802.1p? classification is not enabled or fails to classify. 11 = ingress packets on port 1 will be classified as priority 3 queue if ?diffserv? or ?802.1p? classification is not enabled or fails to classify. note: ?diffserv?, ?802.1p? and port priority can be enabled at the same time. the or?ed result of 802.1p and dscp overwrites the port priority. 2 0 rw tag insertion 1 = when packets are output on the por t, the switch will add 802.1p/q tags to packets without 802.1p/q tags when received. the switch will not add tags to packets already tagged. the tag inserted is the ingress port?s ?port vid?. 0 = disable tag insertion 1 0 rw tag removal 1 = when packets are output on the por t, the switch will remove 802.1p/q tags from packets with 802.1p/q tags when received. the switch will not modify packets received without tags. 0 = disable tag removal 0 0 rw tx multiple queues select enable 1 = the port output queue is split into four priority queues. 0 = single output queue on the port. there is no priority differentiation even though packets are classified into high or low priority.
micrel, inc. ksz8842-pmql/pmbl october 2007 75 m9999-100207-1. 5 port 1 control register 2 (offset 0x0502): p1cr2 this register contains the global per port control for the switch port 1 function. bit default r/w description 15 0 rw reserved 14 0 rw ingress vlan filtering 1 = the switch will discard packets whose vid port membership in vlan table bits [18:16] does not include the ingress port. 0 = no ingress vlan filtering. 13 0 rw discard non pvid packets 1 = the switch will discard packets whose vid does not match ingress port default vid. 0 = no packets will be discarded. 12 0 rw force flow control 1 = will always enable flow control on the port, regardless of an result. 0 = the flow control is enabled based on an result. 11 0 rw back pressure enable 1 = enable port?s half duplex back pressure 0 = disable port?s half duplex back pressure. 10 1 rw transmit enable 1 = enable packet transmission on the port 0 = disable packet transmission on the port 9 1 rw receive enable 1 = enable packet reception on the port 0 = disable packet reception on the port 8 0 rw learning disable 1 = disable switch address learning capability 0 = enable switch address learning 7 0 rw sniffer port 1 = port is designated as sniffer por t and will transmit packets that are monitored. 0 = port is a normal port 6 0 rw receive sniff 1 = all the packets received on the port will be marked as ?monitored packets? and forwarded to the designated ?sniffer port? 0 = no receive monitoring 5 0 rw transmit sniff 1 = all the packets transmitted on the port will be marked as ?monitored packets? and forwarded to the designated ?sniffer port? 0 = no transmit monitoring 4 0 rw reserved 3 0 r/w user priority field 1 = if the packet?s ?user priority field? is greater than the ?user priority bits? in port 1?s vid control register bits [15:13], replace the packet?s ?user priority field? with the ?user priority bits? in port 1?s vid control register bits [15:13]. 0 = do not compare and replace the packet?s ?user priority field?
micrel, inc. ksz8842-pmql/pmbl october 2007 76 m9999-100207-1. 5 bit default r/w description 2 ? 0 111 rw port vlan membership define the port?s port vlan membership. bit 2 stands for the host port, bit 1 for port 2, and bit 0 for port 1. the port can only communicate within the membership. an ?1? includes a port in the membership; an ?0? excludes a port from the membership. port 1 vid control register (offset 0x0504): p1vidcr this register contains the global per port control for the switch port 1 function. bit default r/w description 15-13 000 rw user priority bits port 1 tag [15-13] for priority 12 0 rw cfi bit port 1 tag [12] for cfi 11-0 0x001 rw vid port 1 tag [11-0] for vid note: p1vidcr serve two purposes: (1) associated with the ingress untagged packets, and used for egress tagging. (2) default vid for the ingress untagged or null-vid-tagged packets, and used for address look up. port 1 control register 3 (offset 0x0506): p1cr3 this register contains the port 1 control register for the switch port 1 function. bit default r/w description 15 ? 5 00000000000 ro reserved 4 0 rw reserved 3:2 00 rw ingress limit mode. these bits determine what kinds of frames are limited and counted against ingress limiting as follows: 00 = limit and count all frames 01 = limit and count broadcast, multicast, and flooded unicast frames 10 = limit and count broadcas t and multicast frames only 11 = limit and count broadcast frames only 1 0 rw count ifg bytes 1 = each frame?s minimum inter frame gap (ifg) bytes (12 per frame) are included in ingress and egress rate limiting calculations. 0 = ifg bytes are not counted 0 0 rw count preamble bytes 1 = each frame?s preamble bytes (8 per frame) are included in ingress and egress rate limiting calculations. 0 = preamble bytes are not counted
micrel, inc. ksz8842-pmql/pmbl october 2007 77 m9999-100207-1. 5 port 1 ingress rate control register (offset 0x0508): p1ircr this register contains the port 1 ingress rate control register for the switch port 1 function. bit default r/w description 15 ? 12 0x0 rw ingress pri3 rate priority 3 frames will be discarded after the ingress rate selected as shown below, is reached or exceeded: 0000 =not limited (default) 0001 = 64 kbps 0010 = 128 kbps 0011 = 256 kbps 0100 = 512 kbps 0101 = 1 mbps 0110 = 2 mbps 0111 = 4 mbps 1000 = 8 mbps 1001 = 16 mbps 1010 = 32 mbps 1011 = 48 mbps 1100 = 64 mbps 1101 = 72 mbps 1110 = 80 mbps 1111 = 88 mbps note: for 10base-t, rate settings above 10mbps are set to the default value 0000 (not limited). 11 ? 8 0x0 rw ingress pri2 rate priority 2 frames will be discarded after the ingress rate selected as shown below, is reached or exceeded: 0000 = not limited (default) 0001 = 64 kbps 0010 = 128 kbps 0011 = 256 kbps 0100 = 512 kbps 0101 = 1 mbps 0110 = 2 mbps 0111 = 4 mbps 1000 = 8 mbps 1001 = 16 mbps 1010 = 32 mbps 1011 = 48 mbps 1100 = 64 mbps 1101 = 72 mbps 1110 = 80 mbps 1111 = 88 mbps note: for 10base-t, rate settings above 10mbps are set to the default value 0000 (not limited).
micrel, inc. ksz8842-pmql/pmbl october 2007 78 m9999-100207-1. 5 bit default r/w description 7 ? 4 0x0 rw ingress pri1 rate priority 1 frames will be discarded after the ingress rate selected as shown below, is reached or exceeded: 0000 = not limited (default) 0001 = 64 kbps 0010 = 128 kbps 0011 = 256 kbps 0100 = 512 kbps 0101 = 1 mbps 0110 = 2 mbps 0111 = 4 mbps 1000 = 8 mbps 1001 = 16 mbps 1010 = 32 mbps 1011 = 48 mbps 1100 = 64 mbps 1101 = 72 mbps 1110 = 80 mbps 1111 = 88 mbps note: for 10base-t, rate settings above 10mbps are set to the default value 0000 (not limited). 3 ? 0 0x0 rw ingress pri0 rate priority 0 frames will be discarded after the ingress rate selected as shown below, is reached or exceeded: 0000 = not limited (default) 0001 = 64 kbps 0010 = 128 kbps 0011 = 256 kbps 0100 = 512 kbps 0101 = 1 mbps 0110 = 2 mbps 0111 = 4 mbps 1000 = 8 mbps 1001 = 16 mbps 1010 = 32 mbps 1011 = 48 mbps 1100 = 64 mbps 1101 = 72 mbps 1110 = 80 mbps 1111 = 88 mbps note: for 10base-t, rate settings above 10mbps are set to the default value 0000 (not limited).
micrel, inc. ksz8842-pmql/pmbl october 2007 79 m9999-100207-1. 5 port 1 egress rate control register (offset 0x050a): p1ercr this register contains the port 1 egress rate co ntrol register for the switch port 1 function. bit default r/w description 15 ? 12 0x0 rw egress pri3 rate egress data rate limit for priority 3 frames. output traffic from this priority que ue is shaped according to the egress rate selected as shown below: 0000 = not limited (default) 0001 = 64 kbps 0010 = 128 kbps 0011 = 256 kbps 0100 = 512 kbps 0101 = 1 mbps 0110 = 2 mbps 0111 = 4 mbps 1000 = 8 mbps 1001 = 16 mbps 1010 = 32 mbps 1011 = 48 mbps 1100 = 64 mbps 1101 = 72 mbps 1110 = 80 mbps 1111 = 88 mbps note: for 10base-t, rate settings above 10mbps are set to the default value 0000 (not limited). note: when multiple queue select enable is off (only 1 queue per port), rate limiting applies only to priority 0 queue. 11 ? 8 0x0 rw egress pri2 rate egress data rate limit for priority 2 frames. output traffic from this priority que ue is shaped according to the egress rate selected as shown below: 0000 = not limited (default) 0001 = 64 kbps 0010 = 128 kbps 0011 = 256 kbps 0100 = 512 kbps 0101 = 1 mbps 0110 = 2 mbps 0111 = 4 mbps 1000 = 8 mbps 1001 = 16 mbps 1010 = 32 mbps 1011 = 48 mbps 1100 = 64 mbps 1101 = 72 mbps 1110 = 80 mbps
micrel, inc. ksz8842-pmql/pmbl october 2007 80 m9999-100207-1. 5 bit default r/w description 1111 = 88 mbps note: for 10base-t, rate settings above 10mbps are set to the default value 0000 (not limited). note: when multiple queue select enable is off (only 1 queue per port), rate limiting applies only to priority 0 queue. 7 ? 4 0x0 rw egress pri1 rate egress data rate limit for priority 1 frames. output traffic from this priority que ue is shaped according to the egress rate selected as shown below: 0000 = not limited (default) 0001 = 64 kbps 0010 = 128 kbps 0011 = 256 kbps 0100 = 512 kbps 0101 = 1 mbps 0110 = 2 mbps 0111 = 4 mbps 1000 = 8 mbps 1001 = 16 mbps 1010 = 32 mbps 1011 = 48 mbps 1100 = 64 mbps 1101 = 72 mbps 1110 = 80 mbps 1111 = 88 mbps note: for 10base-t, rate settings above 10mbps are set to the default value 0000 (not limited). note: when multiple queue select enable is off (only 1 queue per port), rate limiting applies only to priority 0 queue. 3 ? 0 0x0 rw egress pri0 rate egress data rate limit for priority 0 frames. output traffic from this priority que ue is shaped according to the egress rate selected as shown below: 0000 = not limited (default) 0001 = 64 kbps 0010 = 128 kbps 0011 = 256 kbps 0100 = 512 kbps 0101 = 1 mbps 0110 = 2 mbps 0111 = 4 mbps 1000 = 8 mbps 1001 = 16 mbps 1010 = 32 mbps
micrel, inc. ksz8842-pmql/pmbl october 2007 81 m9999-100207-1. 5 bit default r/w description 1011 = 48 mbps 1100 = 64 mbps 1101 = 72 mbps 1110 = 80 mbps 1111 = 88 mbps note: for 10base-t, rate settings above 10mbps are set to the default value 0000 (not limited). note: when multiple queue select enable is off (only 1 queue per port), rate limiting applies only to priority 0 queue. port 1 phy special control/status, linkmd (offset 0x0510): p1scslmd this register contains the port linkmd contro l register for the switch port 1 function. bit default r/w description is the same as: 15 0 ro vct 10m short less than 10 meter short p1vct, bit 12 14 ? 13 0 ro vct result [00] = normal condition [01] = open condition has been detected in cable [10] = short condition has been detected in cable [11] = cable diagnostic test is failed p1vct, bits 14-13 12 0 rw sc vct enable 1 = the cable diagnostic test is enabled. it?ll be self- cleared after vct test is done 0 = it indicates the cabl e diagnostic test is completed and the status information is valid for read p1vct, bit 15 11 0 rw force link 1 = force link pass 0 = normal operation p1phyctrl, bit 3 10 1 rw power saving 1 = disable 0 = enable power saving p1phyctrl, bit 2 9 0 rw remote loop back 1 = loop back at pmd/pma of port 1?s phy 0 = normal operation. p1phyctrl, bit 1 8 ? 0 0x000 ro vct fault count distance to the fault. the distance is approximately 0.4mxvct_fault_count p1vct, bits 8-0
micrel, inc. ksz8842-pmql/pmbl october 2007 82 m9999-100207-1. 5 port 1 control register 4 (offset 0x0512): p1cr4 this register contains the global per port control for the switch port 1 function. bit default r/w description is the same as: 15 0 rw led off 1 = turn off all port 1?s leds (led1_3, led1_2, led1_1, led1_0). these pin/balls will be driven high if this bit is set to one. 0 = normal operation p1mbcr, bit 0 14 0 rw txids 1 = disable port?s transmitter 0 = normal operation p1mbcr, bit 1 13 0 rw restart an 1 = restart auto-negotiation 0 = normal operation p1mbcr, bit 9 12 0 rw disable far end fault 1 = disable far end fault detection & pattern transmission. 0 = enable far end fault detection & pattern transmission. p1mbcr, bit 2 11 0 rw power down 1 = power down 0 = normal operation p1mbcr, bit 11 10 0 rw disable auto mdi/mdix 1 = disable auto mdi/mdix function 0 = enable auto mdi/mdix function p1mbcr, bit 3 9 0 rw force mdix 1 = if auto mdi/mdix is disabled, force phy into mdix mode 0 = do not force ph y into mdix mode p1mbcr, bit 4 8 0 loop back 1 = perform loop back, as indicated: start: rxp2/rxm2 (port 2) loop back: pmd/pma of port 1?s phy end: txp2/txm2 (port 2) 0 = normal operation p1mbcr, bit 14 7 1 rw auto negotiation enable 0 = disable auto negotiation, speed and duplex are decided by bit 6 and 5 of the same register. 1 = auto negotiation is on p1mbcr, bit 12 6 0 rw force speed 1 = force 100base-t if an is disabled (bit 7) 0 = force 10base-t if an is disabled (bit 7) p1mbcr, bit 13 5 0 rw force duplex 1 = force full duplex if (1) an is disabled or (2) an is enabled but failed. 0 = force half duplex if (1) an is disabled or (2) an is enabled but failed. p1mbcr, bit 9
micrel, inc. ksz8842-pmql/pmbl october 2007 83 m9999-100207-1. 5 bit default r/w description is the same as: 4 1 rw advertised flow control capability 1 = advertise flow control (pause) capability 0 = suppress flow control (pause) capability from transmission to link partner p1anar, bit 4 3 1 rw advertised 100bt ful l duplex capability 1 = advertise 100base-t full duplex capability 0 = suppress 100base-t full duplex capability from transmission to link partner p1anar, bit 3 2 1 rw advertised 100bt ha lf duplex capability 1 = advertise 100base-t half duplex capability 0 = suppress 100base-t half duplex capability from transmission to link partner p1anar, bit 2 1 1 rw advertised 10bt ful l duplex capability 1 = advertise 10base-t full duplex capability 0 = suppress 10base-t full duplex capability from transmission to link partner p1anar, bit 1 0 1 rw advertised 10bt half duplex capability 1 = advertise 10base-t half duplex capability 0 = suppress 10base-t half duplex capability from transmission to link partner p1anar, bit 0 port 1 status register (offset 0x0514): p1sr this register contains the global per port status for the switch port 1 function. bit default r/w description is the same as: 15 0 rw hp_mdix 1 = hp auto mdix mode 0 = micrel auto mdix mode p1mbcr, bit 5 14 0 ro reserved 13 0 ro polarity reverse 1 = polarity is reversed 0 = polarity is not reversed p1phyctrl, bit 5 12 0 ro receive flow control enable 1 = receive flow control feature is active 0 = receive flow control feature is inactive 11 0 ro transmit flow control enable 1 = transmit flow control feature is active 0 = transmit flow control feature is inactive 10 0 ro operation speed 1 = link speed is 100mbps 0 = link speed is 10mbps 9 0 ro operation duplex 1 = link duplex is full 0 = link duplex is half 8 0 ro far end fault 1 = far end fault status detected 0 = no far end fault status detected p1mbsr, bit 4
micrel, inc. ksz8842-pmql/pmbl october 2007 84 m9999-100207-1. 5 bit default r/w description is the same as: 7 0 ro mdix status 1 = mdi 0 = mdix p1phyctrl,7 bit 4 6 0 ro an done 1 = an done 0 = an not done p1mbsr, bit 5 5 0 ro link good 1 = link good 0 = link not good p1mbsr, bit 2 4 0 ro partner flow control capability 1 = link partner flow control (pause) capable 0 = link partner not flow control (pause) capable p1anlpr, bit 10 3 0 ro partner 100bt full duplex capability 1 = link partner 100base-t full duplex capable 0 = link partner not 100base-t full duplex capable p1anlpr, bit 8 2 0 ro partner 100bt half duplex capability 1 = link partner 100base-t half duplex capable 0 = link partner not 100base-t half duplex capable p1anlpr, bit 7 1 0 ro partner 10bt full duplex capability 1 = link partner 10base-t full duplex capable 0 = link partner not 10base-t full duplex capable p1anlpr, bit 6 0 0 ro partner 10bt half duplex capability 1 = link partner 10base-t half duplex capable 0 = link partner not 10base-t half duplex capable p1anlpr, bit 5 port 1 reserved (offset 0x0516 ? 0x051a) bit default r/w description 15 ? 0 0x0000 ro reserved port 2 control register 1 (offset 0x0520): p2cr1 this register contains the global per port control for the switch port 2 function. bit default r/w description 15 ? 8 0x00 ro reserved 7 0 rw broadcast storm protection enable 1 = enable broadcast storm protecti on for ingress packets on the port 0 = disable broadcast storm protection 6 0 rw diffserv priority classification enable 1 = enable diffserv priority classification for ingress packets on port 0 = disable diffserv function 5 0 rw 802.1p priority classification enable 1 = enable 802.1p priority classification for ingress packets on port 0 = disable 802.1p 4 ? 3 00 rw port based priority classification 00 = ingress packets on port 1 will be classified as priority 0 queue if ?diffserv? or ?802.1p? classification is not enabled or fails to classify. 01 ingress packets on port 1 will be classified as priority 1 queue if
micrel, inc. ksz8842-pmql/pmbl october 2007 85 m9999-100207-1. 5 bit default r/w description ?diffserv? or ?802.1p? classification is not enabled or fails to classify. 10 = ingress packets on port 1 will be classified as priority 2 queue if ?diffserv? or ?802.1p? classification is not enabled or fails to classify. 11 = ingress packets on port 1 will be classified as priority 3 queue if ?diffserv? or ?802.1p? classification is not enabled or fails to classify. note: ?diffserv?, ?802.1p? and port priority can be enabled at the same time. the or?ed result of 802.1p and dscp overwrites the port priority. 2 0 rw tag insertion 1 = when packets are output on the por t, the switch will add 802.1p/q tags to packets without 802.1p/q tags when received. the switch will not add tags to packets already tagged. the tag inserted is the ingress port?s ?port vid?. 0 = disable tag insertion 1 0 rw tag removal 1 = when packets are output on the por t, the switch will remove 802.1p/q tags from packets with 802.1p/q tags when received. the switch will not modify packets received without tags. 0 = disable tag removal 0 0 rw tx multiple queues select enable 1 = the port output queue is split into four priority queues. 0 = single output queue on the port. there is no priority differentiation even though packets are classified into high or low priority. port 2 control register 2 (offset 0x0522): p2cr2 this register contains the global per port control for the switch port 2 function. bit default r/w description 15 reserved reserved reserved 14 0 rw ingress vlan filtering 1 = the switch will discard packets whose vid port membership in vlan table bits [18:16] does not include the ingress port. 0 = no ingress vlan filtering. 13 0 rw discard non pvid packets 1 = the switch will discard packets whose vid does not match ingress port default vid. 0 = no packets will be discarded. 12 0 rw force flow control 1 = will always enable flow control on the port, regardless of an result. 0 = the flow control is enabled based on an result. 11 0 rw back pressure enable 1 = enable port?s half duplex back pressure 0 = disable port?s half duplex back pressure. 10 1 rw transmit enable 1 = enable packet transmission on the port 0 = disable packet transmission on the port 9 1 rw receive enable 1 = enable packet reception on the port 0 = disable packet reception on the port
micrel, inc. ksz8842-pmql/pmbl october 2007 86 m9999-100207-1. 5 bit default r/w description 8 0 rw learning disable 1 = disable switch address learning capability 0 = enable switch address learning 7 0 rw sniffer port 1 = port is designated as sniffer por t and will transmit packets that are monitored. 0 = port is a normal port 6 0 rw receive sniff 1 = all the packets received on the port will be marked as ?monitored packets? and forwarded to the designated ?sniffer port? 0 = no receive monitoring 5 0 rw transmit sniff 1 = all the packets transmitted on t he port will be marked as ?monitored packets? and forwarded to the designated ?sniffer port? 0 = no transmit monitoring 4 0 rw reserved 3 0 r/w user priority field 1 = if the packet?s ?user priority field? is greater than the ?user priority bits? in port 2?s vid control register bits [15:13], replace the packet?s ?user priority field? with the ?user priority bi ts? in port 2?s vid control register bits [15:13]. 0 = do not compare and replace the packet?s ?user priority field? 2 ? 0 111 rw port vlan membership define the port?s port vlan membership . bit 2 stands for port 3, bit 1 for port 2, and bit 0 for port 1. the port can only communicate within the membership. an ?1? includes a port in the membership; an ?0? excludes a port from the membership. port 2 vid control register (offset 0x0524): p2vidcr this register contains the global per port control for the switch port 2 function. bit default r/w description 15 ? 13 000 rw user priority bits port 2 tag [15-13] for priority 12 0 rw cfi bit port 2 tag [12] for cfi 11 ? 0 0x001 rw vid bits port 2 tag [11-0] for vid note: p2vidcr serve two purposes: (1) associated with the ingress untagged packets, and used for egress tagging. (2) default vid for the ingress untagged or null-vid-tagged packets, and used for address look up.
micrel, inc. ksz8842-pmql/pmbl october 2007 87 m9999-100207-1. 5 port 2 control register 3 (offset 0x0526): p2cr3 this register contains the control re gister for the switch port 2 function. bit default r/w description 15 ? 5 000 ro reserved 4 3 ? 2 00 rw ingress limit mode these bits determine what kinds of fr ames are limited and counted against ingress limiting as follows: 00 = limit and count all frames 01 = limit and count broadcast, m ulticast, and flooded unicast frames 10 = limit and count broadcast and multicast frames only 11 = limit and count broadcast frames only 1 0 rw count ifg bytes 1 = each frame?s minimum inter frame gap (ifg) bytes (12 per frame) are included in ingress and egress rate limiting calculations. 0 = ifg bytes are not counted 0 0 rw count preamble bytes. 1 = each frame?s preamble bytes (8 per frame) are included in ingress and egress rate limiting calculations. 0 = preamble bytes are not counted port 2 ingress rate control register (offset 0x0528): p2ircr this register contains the port 2 ingress rate control register for the switch port 2 function. bit default r/w description 15 ? 12 0x0 rw ingress pri3 rate priority 3 frames will be discarded after the ingress rate selected as shown below, is reached or exceeded: 0000 = not limited (default) 0001 = 64 kbps 0010 = 128 kbps 0011 = 256 kbps 0100 = 512 kbps 0101 = 1 mbps 0110 = 2 mbps 0111 = 4 mbps 1000 = 8 mbps 1001 = 16 mbps 1010 = 32 mbps 1011 = 48 mbps 1100 = 64 mbps 1101 = 72 mbps 1110 = 80 mbps 1111 = 88 mbps note: for 10base-t, rate settings above 10mbps are set to the default value 0000 (not limited).
micrel, inc. ksz8842-pmql/pmbl october 2007 88 m9999-100207-1. 5 bit default r/w description 11 ? 8 0x0 rw ingress pri2 rate priority 2 frames will be discarded after the ingress rate selected as shown below, is reached or exceeded: 0000 = not limited (default) 0001 = 64 kbps 0010 = 128 kbps 0011 = 256 kbps 0100 = 512 kbps 0101 = 1 mbps 0110 = 2 mbps 0111 = 4 mbps 1000 = 8 mbps 1001 = 16 mbps 1010 = 32 mbps 1011 = 48 mbps 1100 = 64 mbps 1101 = 72 mbps 1110 = 80 mbps 1111 = 88 mbps note: for 10base-t, rate settings above 10mbps are set to the default value 0000 (not limited). 7 ? 4 0x0 rw ingress pri1 rate priority 1 frames will be discarded after the ingress rate selected as shown below, is reached or exceeded: 0000 = not limited (default) 0001 = 64 kbps 0010 = 128 kbps 0011 = 256 kbps 0100 = 512 kbps 0101 = 1 mbps 0110 = 2 mbps 0111 = 4 mbps 1000 = 8 mbps 1001 = 16 mbps 1010 = 32 mbps 1011 = 48 mbps 1100 = 64 mbps 1101 = 72 mbps 1110 = 80 mbps 1111 = 88 mbps note: for 10base-t, rate settings above 10mbps are set to the default value 0000 (not limited).
micrel, inc. ksz8842-pmql/pmbl october 2007 89 m9999-100207-1. 5 bit default r/w description 3 ? 0 0x0 rw ingress pri0 rate priority 0 frames will be discarded after the ingress rate selected as shown below, is reached or exceeded: 0000 = not limited (default) 0001 = 64 kbps 0010 = 128 kbps 0011 = 256 kbps 0100 = 512 kbps 0101 = 1 mbps 0110 = 2 mbps 0111 = 4 mbps 1000 = 8 mbps 1001 = 16 mbps 1010 = 32 mbps 1011 = 48 mbps 1100 = 64 mbps 1101 = 72 mbps 1110 = 80 mbps 1111 = 88 mbps note: for 10base-t, rate settings above 10mbps are set to the default value 0000 (not limited). port 2 egress rate control register (offset 0x052a): p2ercr this register contains the port 2 egress rate co ntrol register for the switch port 2 function. bit default def r/w description 15 ? 12 0x0 0 rw egress pri3 rate egress data rate limit for priority 3 frames. output traffic from this priority queue is shaped according to the egress rate selected as shown below: 0000 = not limited (default) 0001 = 64 kbps 0010 = 128 kbps 0011 = 256 kbps 0100 = 512 kbps 0101 = 1 mbps 0110 = 2 mbps 0111 = 4 mbps 1000 = 8 mbps 1001 = 16 mbps 1010 = 32 mbps 1011 = 48 mbps 1100 = 64 mbps 1101 = 72 mbps 1110 = 80 mbps 1111 = 88 mbps
micrel, inc. ksz8842-pmql/pmbl october 2007 90 m9999-100207-1. 5 bit default def r/w description note: for 10base-t, rate settings above 10mbps are set to the default value 0000 (not limited). note: when multiple queue select enable is off (only 1 queue per port), rate limiting applies only to priority 0 queue. 11 ? 8 0x0 0 rw egress pri2 rate egress data rate limit for priority 2 frames. output traffic from this priority que ue is shaped according to the egress rate selected as shown below: 0000 = not limited (default) 0001 = 64 kbps 0010 = 128 kbps 0011 = 256 kbps 0100 = 512 kbps 0101 = 1 mbps 0110 = 2 mbps 0111 = 4 mbps 1000 = 8 mbps 1001 = 16 mbps 1010 = 32 mbps 1011 = 48 mbps 1100 = 64 mbps 1101 = 72 mbps 1110 = 80 mbps 1111 = 88 mbps note: for 10base-t, rate settings above 10mbps are set to the default value 0000 (not limited). note: when multiple queue select enable is off (only 1 queue per port), rate limiting applies only to priority 0 queue. 7 ? 4 0x0 0 rw egress pri2 rate egress data rate limit for priority 2 frames. output traffic from this priority queue is shaped according to the egress rate selected as shown below: 0000 = not limited (default) 0001 = 64 kbps 0010 = 128 kbps 0011 = 256 kbps 0100 = 512 kbps 0101 = 1 mbps 0110 = 2 mbps 0111 = 4 mbps 1000 = 8 mbps 1001 = 16 mbps 1010 = 32 mbps 1011 = 48 mbps 1100 = 64 mbps
micrel, inc. ksz8842-pmql/pmbl october 2007 91 m9999-100207-1. 5 bit default def r/w description 1101 = 72 mbps 1110 = 80 mbps 1111 = 88 mbps note: for 10base-t, rate settings above 10mbps are set to the default value 0000 (not limited). note: when multiple queue select enable is off (only 1 queue per port), rate limiting applies only to priority 0 queue. 3 ? 0 0x0 0 rw egress pri0 rate egress data rate limit for priority 0 frames. output traffic from this priority queue is shaped according to the egress rate selected as shown below: 0000 = not limited (default) 0001 = 64 kbps 0010 = 128 kbps 0011 = 256 kbps 0100 = 512 kbps 0101 = 1 mbps 0110 = 2 mbps 0111 = 4 mbps 1000 = 8 mbps 1001 = 16 mbps 1010 = 32 mbps 1011 = 48 mbps 1100 = 64 mbps 1101 = 72 mbps 1110 = 80 mbps 1111 = 88 mbps note: for 10base-t, rate settings above 10mbps are set to the default value 0000 (not limited). note: when multiple queue select enable is off (only 1 queue per port), rate limiting applies only to priority 0 queue.
micrel, inc. ksz8842-pmql/pmbl october 2007 92 m9999-100207-1. 5 port 2 phy special control/status, linkmd (offset 0x0530): p2scslmd this register contains the port 2 linkmd cont rol register for the switch port 2 function. bit default r/w description is the same as: 15 0 ro vct 10m short less than 10 meter short p2vct, bit 12 14:13 0 ro vct result [00] = normal condition [01] = open condition has been detected in cable [10] = short condition has been detected in cable [11] = cable diagnostic test is failed p2vct, bits 14-13 12 0 rw sc (self- clear) vct enable 1 = the cable diagnostic test is enabled. it?ll be self- cleared after vct test is done 0 = it indicates the cable diagnostic test is completed and the status information is valid for read p2vct, bit 15 11 0 rw force link 1 = force link pass 0 = normal operation p2phyctrl, bit 3 10 1 rw power saving 1 = disable 0 = enable power saving p2phyctrl, bit 2 9 0 rw remote loop back >> 1 = loop back at pmd/pma of port 2?s phy end: txp2/txm2 (port 2) 0 = normal operation. p2phyctrl, bit 1 8 ? 0 0 ro vct fault count distance to the fault. it?s approximately 0.4m*vct_fault_count p2vct, bits 8-0 port 2 control register 4 (offset 0x0532): p2cr4 this register contains the global per port control for the switch port 2 function. bit default r/w description is the same as: 15 0 rw led off 1 = turn off all port 2?s leds (led2_3, led2_2, led2_1, led2_0. these pin/balls will be driven high if this bit is set to one. 0 = normal operation p2mbcr, bit 0 14 0 rw txids 1 = disable port?s transmitter 0 = normal operation p2mbcr, bit 1 13 0 rw restart an 1 = restart auto-negotiation 0 = normal operation p2mbcr, bit 9 12 0 rw disable far end fault 1 = disable far end fault detection & pattern transmission. 0 = enable far end fault detection & pattern transmission. p2mbcr, bit 2
micrel, inc. ksz8842-pmql/pmbl october 2007 93 m9999-100207-1. 5 bit default r/w description is the same as: 11 0 rw power down 1 = power down 0 = normal operation p2mbcr, bit 11 10 0 rw disable auto mdi/mdix 1 = disable auto mdi/mdix function 0 = enable auto mdi/mdix function p2mbcr, bit 3 9 0 rw force mdix 1 = if auto mdi/mdix is disabled, force phy into mdix mode 0 = do not force phy into mdix mode p2mbcr, bit 4 8 0 rw loop back 1 = perform loop back, as indicated: start: rxp1/rxm1 (port 1) loop back: pmd/pma of port 2?s phy end: txp1/txm1 (port 1) 0 = normal operation p2mbcr, bit 14 7 1 rw auto negotiation enable 0 = disable auto negotiation, speed and duplex are decided by bit 6 and 5 of the same register. 1 = auto negotiation is on p2mbcr, bit 12 6 0 rw force speed 1 = force 100base-t if an is disabled (bit 7) 0 = force 10base-t if an is disabled (bit 7) p2mbcr, bit 13 5 0 rw force duplex 1 = force full duplex if (1) an is disabled or (2) an is enabled but failed. 0 = force half duplex if (1) an is disabled or (2) an is enabled but failed. p2mbcr, bit 9 4 1 rw advertised flow control capability 1 = advertise flow control (pause) capability 0 = suppress flow control (pause) capability from transmission to link partner p1anar, bit 4 3 1 rw advertised 100bt ful l duplex capability 1 = advertise 100base-t full duplex capability 0 = suppress 100base-t full duplex capability from transmission to link partner p1anar, bit 3 2 1 rw advertised 100bt ha lf duplex capability 1 = advertise 100base-t half duplex capability 0 = suppress 100base-t half duplex capability from transmission to link partner p1anar, bit 2 1 1 rw advertised 10bt ful l duplex capability 1 = advertise 10base-t full duplex capability 0 = suppress 10base-t full duplex capability from transmission to link partner p1anar, bit 1 0 1 rw advertised 10bt half duplex capability 1 = advertise 10base-t half duplex capability 0 = suppress 10base-t half duplex capability from transmission to link partner p1anar, bit 0
micrel, inc. ksz8842-pmql/pmbl october 2007 94 m9999-100207-1. 5 port 2 status register (offset 0x0534): p2sr this register contains the global per port status for the switch port 2 function. bit default r/w description is the same as: 15 0 rw hp_mdix 1 = hp auto mdix mode 0 = micrel auto mdix mode p2mbcr, bit 5 14 0 ro reserved 13 0 ro polarity reverse 1 = polarity is reversed 0 = polarity is not reversed p2phyctrl, bit 5 12 0 ro receive flow control enable 1 = receive flow control feature is active 0 = receive flow control feature is inactive 11 0 ro transmit flow control enable 1 = transmit flow control feature is active 0 = transmit flow control feature is inactive 10 0 ro operation speed 1 = link speed is 100mbps 0 = link speed is 10mbps 9 0 ro operation duplex 1 = link duplex is full 0 = link duplex is half 8 0 ro far end fault 1 = far end fault status detected 0 = no far end fault status detected p2mbcr, bit 4 7 0 ro mdix status 1 = mdix 0 = mdi p2phyctrl, bit 4 6 0 ro an done 1 = an done 0 = an not done p2mbsr, bit 5 5 0 ro link good 1 = link good 0 = link not good p2mbsr, bit 2 4 0 ro partner flow control capability 1 = link partner flow control (pause) capable 0 = link partner not flow control (pause) capable p2anlpr, bit 10 3 0 ro partner 100bt full duplex capability 1 = link partner 100base-t full duplex capable 0 = link partner not 100base-t full duplex capable p2anlpr, bit 8 2 0 ro partner 100bt half duplex capability 1 = link partner 100base-t half duplex capable 0 = link partner not 100base-t half duplex capable p2anlpr, bit 7 1 0 ro partner 10bt full duplex capability 1 = link partner 10base-t full duplex capable 0 = link partner not 10base-t full duplex capable p2anlpr, bit 6
micrel, inc. ksz8842-pmql/pmbl october 2007 95 m9999-100207-1. 5 bit default r/w description is the same as: 0 0 ro partner 10bt half duplex capability 1 = link partner 10base-t half duplex capable 0 = link partner not 10b ase-t half duplex capable p2anlpr, bit 5 port 2 reserved (offset 0x0536 ? 0x053a) this register is reserved. bit default r/w description 15 ? 0 0x0000 ro reserved host control register 1 (offset 0x0540): p3cr1 this register contains the global per port control for the switch host port function. bit default r/w description 15 ? 8 0x00 ro reserved 7 0 rw broadcast storm protection enable 1 = enable broadcast storm protect ion for ingress packets on the port 0 = disable broadcast storm protection 6 0 rw diffserv priority classification enable 1 = enable diffserv priority classification for ingress packets on port 0 = disable diffserv function 5 0 rw 802.1p priority classification enable 1 = enable 802.1p priority classification for ingress packets on port 0 = disable 802.1p 4 ? 3 00 rw port based priority classification 00 = ingress packets on port 1 will be classified as priority 0 queue if ?diffserv? or ?802.1p? classification is not enabled or fails to classify. 01 = ingress packets on port 1 will be classified as priority 1 queue if ?diffserv? or ?802.1p? classification is not enabled or fails to classify. 10 = ingress packets on port 1 will be classified as priority 2 queue if ?diffserv? or ?802.1p? classification is not enabled or fails to classify. 11 = ingress packets on port 1 will be classified as priority 3 queue if ?diffserv? or ?802.1p? classification is not enabled or fails to classify. note: ?diffserv?, ?802.1p? and port priority can be enabled at the same time. the or?ed result of 802.1p and dscp overwrites the port priority. 2 0 rw tag insertion 1 = when packets are output on the por t, the switch will add 802.1p/q tags to packets without 802.1p/q tags when received. the switch will not add tags to packets already tagged. the tag inserted is the ingress port?s ?port vid?. 0 = disable tag insertion 1 0 rw tag removal 1 = when packets are output on the por t, the switch will remove 802.1p/q tags from packets with 802.1p/q tags when received. the switch will not modify packets received without tags. 0 = disable tag removal 0 0 rw tx multiple queues select enable 1 = the port output queue is split into fourpriority queues. 0 = single output queue on the port. there is no priority differentiation even though packets are classified into high or low priority.
micrel, inc. ksz8842-pmql/pmbl october 2007 96 m9999-100207-1. 5 host control register 2 (offset 0x0542): p3cr2 this register contains the global per port control for the switch host port function. bit default r/w description 15 0 rw reserved 14 0 rw ingress vlan filtering 1 = the switch will discard packets whose vid port membership in vlan table bits [18:16] does not include the ingress port. 0 = no ingress vlan filtering. 13 0 rw discard non pvid packets 1 = the switch will discard packets whose vid does not match ingress port default vid. 0 = no packets will be discarded. 12 0 rw reserved. for factory testing purpose only. always write 0. 11 0 rw reserved must be 0 10 1 rw transmit enable 1 = enable packet transmission on the port 0 = disable packet transmission on the port 9 1 rw receive enable 1 = enable packet reception on the port 0 = disable packet reception on the port 8 0 rw learning disable 1 = disable switch address learning capability 0 = enable switch address learning 7 0 rw sniffer port 1 = port is designated as sniffer por t and will transmit packets that are monitored. 0 = port is a normal port 6 0 rw receive sniff 1 = all the packets received on the port will be marked as ?monitored packets? and forwarded to the designated ?sniffer port? 0 = no receive monitoring 5 0 rw transmit sniff 1 = all the packets transmitted on t he port will be marked as ?monitored packets? and forwarded to the designated ?sniffer port? 0 = no transmit monitoring 4 0 rw reserved 3 0 r/w user priority field 1 = if the packet?s ?user priority field? is greater than the ?user priority bits? in host?s vid control register bit s [15:13], replace the packet?s ?user priority field? with the ?user priority bits? in host?s vid control register bits [15:13]. 0 = do not compare and replace the packet?s ?user priority field? 2 ? 0 111 rw port vlan membership define the port?s port vlan membership. bit 2 stands for host port, bit 1 for port 2, and bit 0 for port 1. the port can only communicate within the membership. an ?1? includes a port in the membership; an ?0? excludes a port from the membership.
micrel, inc. ksz8842-pmql/pmbl october 2007 97 m9999-100207-1. 5 host vid control register (offset 0x0544): p3vidcr this register contains the global per port control for the switch host port function. bit default r/w description 15-13 000 rw user priority bits host port default tag bits [15-13] for user priority 12 0 rw cfi bit host port default tag bit 12 for cfi 11-0 0x001 rw vid bits host port default tag bits [11-0] for vid note: p3vidcr serve two purposes: (1) associated with the ingress untagged packets, and used for egress tagging. (2) default vid for the ingress untagged or null-vid-tagged packets, and used for address look up. host control register 3 (offset 0x0546): p3cr3 this register contains the host port control register for the switch host port function. bit default name r/w description 15 ? 5 000 reserved ro reserved 4 0 reserved 3-2 00 0 rw ingress limit mode these bits determine what kinds of frames are limited and counted against ingress limiting as follows: 00 = limit and count all frames 01 = limit and count broadcast, multicast, and flooded unicast frames 10 = limit and count broadcas t and multicast frames only 11 = limit and count broadcast frames only 1 0 0 rw count ifg bytes 1 = each frame?s minimum inter frame gap (ifg) bytes (12 per frame) are included in ingress and egress rate limiting calculations. 0 = ifg bytes are not counted 0 0 0 rw count preamble bytes 1 = each frame?s preamble bytes (8 per frame) are included in ingress and egress rate limiting calculations. 0 = preamble bytes are not counted
micrel, inc. ksz8842-pmql/pmbl october 2007 98 m9999-100207-1. 5 host ingress rate control register (offset 0x0548): p3ircr this register contains the host po rt ingress rate control register for the switch host port function. bit default name r/w description 15 ? 12 0x0 0 rw ingress pri3 rate priority 3 frames will be discarded after the ingress rate selected as shown below, is reached or exceeded: 0000 = not limited (default) 0001 = 64 kbps 0010 = 128 kbps 0011 = 256 kbps 0100 = 512 kbps 0101 = 1 mbps 0110 = 2 mbps 0111 = 4 mbps 1000 = 8 mbps 1001 = 16 mbps 1010 = 32 mbps 1011 = 48 mbps 1100 = 64 mbps 1101 = 72 mbps 1110 = 80 mbps 1111 = 88 mbps note: for 10base-t, rate settings above 10mbps are set to the default value 0000 (not limited). 11 ? 8 0x0 0 rw ingress pri2 rate priority 2 frames will be discarded after the ingress rate selected as shown below, is reached or exceeded: 0000 = not limited (default) 0001 = 64 kbps 0010 = 128 kbps 0011 = 256 kbps 0100 = 512 kbps 0101 = 1 mbps 0110 = 2 mbps 0111 = 4 mbps 1000 = 8 mbps 1001 = 16 mbps 1010 = 32 mbps 1011 = 48 mbps 1100 = 64 mbps 1101 = 72 mbps 1110 = 80 mbps 1111 = 88 mbps note: for 10base-t, rate settings above 10mbps are set to the default value 0000 (not limited).
micrel, inc. ksz8842-pmql/pmbl october 2007 99 m9999-100207-1. 5 bit default name r/w description 7 ? 4 0x0 0 rw ingress pri1 rate priority 1 frames will be discarded after the ingress rate selected as shown below, is reached or exceeded: 0000 = not limited (default) 0001 = 64 kbps 0010 = 128 kbps 0011 = 256 kbps 0100 = 512 kbps 0101 = 1 mbps 0110 = 2 mbps 0111 = 4 mbps 1000 = 8 mbps 1001 = 16 mbps 1010 = 32 mbps 1011 = 48 mbps 1100 = 64 mbps 1101 = 72 mbps 1110 = 80 mbps 1111 = 88 mbps note: for 10base-t, rate settings above 10mbps are set to the default value 0000 (not limited). 3 ? 0 0x0 0 rw ingress pri0 rate priority 0 frames will be discarded after the ingress rate selected as shown below, is reached or exceeded: 0000 = not limited (default) 0001 = 64 kbps 0010 = 128 kbps 0011 = 256 kbps 0100 = 512 kbps 0101 = 1 mbps 0110 = 2 mbps 0111 = 4 mbps 1000 = 8 mbps 1001 = 16 mbps 1010 = 32 mbps 1011 = 48 mbps 1100 = 64 mbps 1101 = 72 mbps 1110 = 80 mbps 1111 = 88 mbps note: for 10base-t, rate settings above 10mbps are set to the default value 0000 (not limited).
micrel, inc. ksz8842-pmql/pmbl october 2007 100 m9999-100207-1. 5 host egress rate control register (offset 0x054a): p3ercr this register contains the host po rt egress rate control register fo r the switch host port function. bit default name r/w description 15 ? 12 0x0 0 rw egress pri3 rate egress data rate limit for priority 3 frames. output traffic from this priority queue is shaped according to the egress rate selected as shown below: 0000 = not limited (default) 0001 = 64 kbps 0010 = 128 kbps 0011 = 256 kbps 0100 = 512 kbps 0101 = 1 mbps 0110 = 2 mbps 0111 = 4 mbps 1000 = 8 mbps 1001 = 16 mbps 1010 = 32 mbps 1011 = 48 mbps 1100 = 64 mbps 1101 = 72 mbps 1110 = 80 mbps 1111 = 88 mbps note: for 10base-t, rate settings above 10mbps are set to the default value 0000 (not limited). note: when multiple queue select enable is off (only 1 queue per port), rate limiting applies only to priority 0 queue. 11 ? 8 0x0 0 rw egress pri2 rate egress data rate limit for priority 2 frames. output traffic from this priority queue is shaped according to the egress rate selected as shown below: 0000 = not limited (default) 0001 = 64 kbps 0010 = 128 kbps 0011 = 256 kbps 0100 = 512 kbps 0101 = 1 mbps 0110 = 2 mbps 0111 = 4 mbps 1000 = 8 mbps 1001 = 16 mbps 1010 = 32 mbps 1011 = 48 mbps 1100 = 64 mbps 1101 = 72 mbps 1110 = 80 mbps 1111 = 88 mbps
micrel, inc. ksz8842-pmql/pmbl october 2007 101 m9999-100207-1. 5 bit default name r/w description note: for 10base-t, rate settings above 10mbps are set to the default value 0000 (not limited). note: when multiple queue select enable is off (only 1 queue per port), rate limiting applies only to priority 0 queue. 7 ? 4 0x0 0 rw egress pri1 rate egress data rate limit for priority 1 frames. output traffic from this priority queue is shaped according to the egress rate selected as shown below: 0000 = not limited (default) 0001 = 64 kbps 0010 = 128 kbps 0011 = 256 kbps 0100 = 512 kbps 0101 = 1 mbps 0110 = 2 mbps 0111 = 4 mbps 1000 = 8 mbps 1001 = 16 mbps 1010 = 32 mbps 1011 = 48 mbps 1100 = 64 mbps 1101 = 72 mbps 1110 = 80 mbps 1111 = 88 mbps note: for 10base-t, rate settings above 10mbps are set to the default value 0000 (not limited). note: when multiple queue select enable is off (only 1 queue per port), rate limiting applies only to priority 0 queue. 3 ? 0 0x0 0 rw egress pri0 rate egress data rate limit for priority 0 frames. output traffic from this priority queue is shaped according to the egress rate selected as shown below: 0000 = not limited (default) 0001 = 64 kbps 0010 = 128 kbps 0011 = 256 kbps 0100 = 512 kbps 0101 = 1 mbps 0110 = 2 mbps 0111 = 4 mbps 1000 = 8 mbps 1001 = 16 mbps 1010 = 32 mbps 1011 = 48 mbps
micrel, inc. ksz8842-pmql/pmbl october 2007 102 m9999-100207-1. 5 bit default name r/w description 1100 = 64 mbps 1101 = 72 mbps 1110 = 80 mbps 1111 = 88 mbps note: for 10base-t, rate settings above 10mbps are set to the default value 0000 (not limited). note: when multiple queue select enable is off (only 1 queue per port), rate limiting applies only to priority 0 queue. reserved (offset 0x0550) this register is reserved. bit default r/w description 15 ? 0 0x0000 ro reserved reserved (offset 0x0554) this register is reserved. bit default r/w description 15 ? 0 0x0000 ro reserved reserved (offset 0x0556) this register is reserved. bit default r/w description 15 ? 0 0x0000 ro reserved reserved (offset 0x0560) this register is reserved for internal testing. bit default r/w description 15 ? 10 0x00 ro reserved 9 ? 0 ? ro reserved
micrel, inc. ksz8842-pmql/pmbl october 2007 103 m9999-100207-1. 5 mib (management information base) counters the ksz8842-pmql/pmbl provides 32 mib counters for port 1, port 2, and the host port. these counters are used to monitor the port activity for network management. the mib c ounters are formatted ?per port? as shown in table 8, and ?per all port dropped packet? as shown in table 8. bit name r/w description default 31 overflow ro 1 = counter overflow. 0 = no counter overflow. 0 30 count valid ro 1 = counter value is valid. 0 = counter value is not valid. 0 29-0 counter values ro counter value 0 table 8. format of per port mib counters ?per port? mib counters are read using i ndirect memory access. the base address offsets and address ranges for both ethernet ports are: port 1, base address of the mib c ounter is 0x00 and range is (0x00-0x1f) as shown in table 9. port 2, base address of the mib c ounter is 0x20 and range is (0x20-0x3f) as refer in table 9. host port, base address of the mib counter is 0x40 and range is (0x40-0x5f) as refer in table 9. per port mib counters read/write functions use access cont rol register iacr (0x04a0) bit 12. the base address offset and address range for port 1 is 0x00 and range is (0x00-0x1f) that can be changed in register iacr (0x04a0) bits[9:0]. the data of mib counters are from the indirect access da ta register iadr4 (0x04a8) and iadr5 (0x04aa) based on table 9. offset counter name description 0x0 (base address) rxloprioritybyte rx lo-priority (defaul t) octet count including bad packets 0x1 rxhiprioritybyte rx hi-priority octet count including bad packets 0x2 rxundersizepkt rx undersize packets w/ good crc 0x3 rxfragments rx fragment packets w/ bad crc, symbol errors or alignment errors 0x4 rxoversize rx oversize packets w/ good crc (max: 1536 or 1522 bytes) 0x5 rxjabbers rx packets longer than 1522 bytes w/ eit her crc errors, alignment errors, or symbol errors (depends on max packet size setting) 0x6 rxsymbolerror rx packets w/ invalid data symbol and legal packet size. 0x7 rxcrcerror rx packets within (64,1522) bytes w/ an integral number of bytes and a bad crc (upper limit depends on max packet size setting) 0x8 rxalignmenterror rx packets within (64,1522) bytes w/ a non-integral number of bytes and a bad crc (upper limit depends on max packet size setting) 0x9 rxcontrol8808pkts number of mac control fram es received by a port with 88-08h in ethertype field 0xa rxpausepkts number of pause frames received by a port. pause frame is qualified with ethertype (88-08h), da, control opcode (00-01) , data length (64b min), and a valid crc 0xb rxbroadcast rx good broadcast packets (not including error broadcast packets or valid multicast packets) 0xc rxmulticast rx good multicast packets (not including ma c control frames, error multicast packets or valid broadcast packets) 0xd rxunicast rx good unicast packets 0xe rx64octets total rx packets (bad packets included) that were 64 octets in length 0xf rx65to127octets total rx packets (bad packets inc luded) that are between 65 and 127 octets in length 0x10 rx128to255octets total rx packets (bad packets included) that are between 128 and 255 octets in
micrel, inc. ksz8842-pmql/pmbl october 2007 104 m9999-100207-1. 5 offset counter name description length 0x11 rx256to511octets total rx packets (bad packets included) that are between 256 and 511 octets in length 0x12 rx512to1023octets total rx packets (bad packets included) that are between 512 and 1023 octets in length 0x13 rx1024to1522octets total rx packets (bad packets included) that are between 1024 and 1522 octets in length (upper limit depends on max packet size setting) 0x14 txloprioritybyte tx lo-priority good octet count, including pause packets 0x15 txhiprioritybyte tx hi-priority good octet count, including pause packets 0x16 txlatecollision the number of times a collision is detected later than 512 bit-times into the tx of a packet 0x17 txpausepkts number of pause frames transmitted by a port 0x18 txbroadcastpkts tx good broadcast packets (not incl uding error broadcast or valid multicast packets) 0x19 txmulticastpkts tx good multicast packets (not including error multicast packets or valid broadcast packets) 0x1a txunicastpkts tx good unicast packets 0x1b txdeferred tx packets by a port for which the 1st tx attempt is delayed due to the busy medium 0x1c txtotalcollision tx total collision, half duplex only 0x1d txexcessivecollision a count of frames fo r which tx fails due to excessive collisions 0x1e txsinglecollision successfully tx frames on a por t for which tx is inhibited by exactly one collision 0x1f txmultiplecollision successfully tx frames on a port for which tx is inhibited by more than one collision table 9. port 1s ?per port? mi b counters indirect memory offsets format of ?all port drop ped packet? mib counters bit default r/w description 30 ? 16 ? n/a reserved 15 ? 0 ? ro counter value table 10. ?all port dropped packet? mib counters format note: ?all port dropped packet? mib counters do not indicate overfl ow or validity; therefore, the application must keep track o f overflow and valid conditions. ?all port dropped packet? mib counters are read using indire ct memory access. the addres s offsets for these counters are shown in table 11. offset counter name description 0x100 port1 tx drop packets tx packets dropped due to lack of resources 0x101 port2 tx drop packets tx packets dropped due to lack of resources 0x103 port1 rx drop packets rx packets dropped due to lack of resources 0x104 port2 rx drop packets rx packets dropped due to lack of resources table 11. ?all port dropped packet? mib counters indirect memory offsets
micrel, inc. ksz8842-pmql/pmbl october 2007 105 m9999-100207-1. 5 examples: 1. mib counter read (read port 1 ?rx64octets? counter at indirect address offset 0x0e) write to reg. iacr with 0x1c0e (set indirect address and trigger a read mib counters operation) then read reg. iadr5 (mib counter value 31-16) // if bit 31 =1, there was a counter overflow // if bit 30 =0, restart (reread) from this register read reg. iadr4 (mib counter value 15-0) 2. mib counter read (read port 2 ?rx64octets? counter at indirect address offset 0x2e) write to reg. iacr with 0x1c2e (set indirect address and trigger a read mib counters operation) then read reg. iadr5 (mib counter value 31-16) // if bit 31 =1, there was a counter overflow // if bit 30 =0, restart (reread) from this register read reg. iadr4 (mib counter value 15-0) 3. mib counter read (read ?port1 tx drop packet s? counter at indirect address offset 0x100) write to reg. iacr with 0x1d00 (set indirect address and trigger a read mib counters operation) then read reg. iadr4 (mib counter value 15-0) additional mib information per port mib counters are designed as ?read clear?. that is, these counters will be cleared after they are read. all port dropped packet mib counters are not cleared after t hey are accessed. the application needs to keep track of overflow and valid conditions on these counters.
micrel, inc. ksz8842-pmql/pmbl october 2007 106 m9999-100207-1. 5 static mac address table the ksz8842-pmql/pmbl supports both a static and a dynamic mac address tabl e. in response to a destination address (da) look up, the ksz8842-pmql/pmbl searches both tables to make a packet forwarding decision. in response to a source address (sa) look up, only the dynamic table is searched for aging, migration and learning purposes. the static da look up result takes precedence over the dy namic da look up result. if there is a da match in both tables, the result from the st atic table is used. these entries in the static table will not be aged out by the ksz8842- pmql/pmbl. bit default r/w description 57 ? 54 0000 rw fid filter vlan id - identifies one of the 16 active vlans. 53 0 r/w use fid 1 =specifies the use of fid+ma c for static table look ups 0 = specifies only the use of mac for static table look ups 52 0 r/w override 1 = overrides the port setting ?transmit enable=0? or ?receive enable=0? setting. 0 = specifies no override 51 0 r/w valid 1 = specifies that this entry is val id, the look up result will be used 0 = specifies that this entry is not valid 50 ? 48 000 r/w forwarding ports these 3 bits control the forwarding port(s): 000 ,no forward 001, forward to port 1 010, forward to port 2 100, forward to port 3 011, forward to port 1 and port 2 110, forward to port 2 and port 3 101, forward to port 1 and port 3 111, broadcasting (excluding the ingress port) 47 ? 0 0 r/w mac address 48 bits mac address table 12. static mac table format (8 entries) examples: 1. static address table read (read the sec ond entry at indirect address offset 0x01) write to reg. iacr with 0x1001 (set indirect add ress and trigger a read stat ic mac table operation) then read reg. iadr3 (static mac table bits 57-48) read reg. iadr2 (static mac table bits 47-32) read reg. iadr5 (static mac table bits 31-16) read reg. iadr4 (static mac table bits 15-0) 2. static address table write (write the eighth entry at indirect address offset 0x07) write to reg. iadr3 (s tatic mac table bits 57-48) write to reg. iadr2 (s tatic mac table bits 47-32) write to reg. iadr5 (s tatic mac table bits 31-16) write to reg. iadr4 (static mac table bits 15-0) write to reg. iacr with 0x0007 (set indirect address and trigger a write static ma c table operation)
micrel, inc. ksz8842-pmql/pmbl october 2007 107 m9999-100207-1. 5 dynamic mac address table the dynamic mac address is a read only table. bit default r/w description 71 ro data not ready 1 = specifies that the entry is not ready, continue retrying until bit is set to 0 0 = specifies that the entry is ready 70 ? 67 ro reserved 66 1 ro mac empty 1 = specifies that there is no valid entry in the table 0 = specifies that there ar e valid entries in the table 65 ? 56 00_0000_0000 ro no of valid entries indicates how many valid entries in the table 0x3ff means 1 k entries 0x001 means 2 entries 0x000 and bit 66 = 0 means 1 entry 0x000 and bit 66 = 1 means 0 entry 55 ? 54 ro time stamp specifies the 2-bit count er for internal aging. 53 ? 52 00 ro source port identifies the source port where fid+mac is learned: 00, port 1 01, port 2 10, port 3 51 ? 48 0x0 ro fid specifies the filter id. 47 ? 0 0x000_0000_0000 ro mac address specifies the 48-bit mac address. table 13. dynamic mac address table format (1024 entries) example: dynamic mac address table read (read the first entry at indirect address offs et 0 and retrieve the mac table size) write to reg. iacr with 0x1800 (set indirect add ress and trigger a read dynam ic mac table operation) then read reg. iadr1 (dynamic mac table bits 71-64) // if bit 71 =1, restart (reread) from this register read reg. iadr3 (dynamic mac table bits 63-48) read reg. iadr2 (dynamic mac table bits 47-32) read reg. iadr5 (dynamic mac table bits 31-16) read reg. iadr4 (dynamic mac table bits 15-0)
micrel, inc. ksz8842-pmql/pmbl october 2007 108 m9999-100207-1. 5 vlan table the ksz8842-pmql/pmbl uses the vlan table to perform look ups. if 802.1q vlan mode is enabled (sgcr2[15]), this table will be used to retrieve t he vlan information that is associated wi th the ingress packet. this information includes fid (filter id), vid (vlan id), a nd vlan membership as described in table 14: bit default r/w description 19 1 rw valid 1 = specifies that this entry is v alid, the look up result will be used 0 = specifies that this entry is not valid 18 ? 16 111 r/w membership specifies which ports are members of the vlan. if a da look up fails (no match in both static and dynamic table s), the packet associated with this vlan will be forwarded to ports specified in this field. for example: 101 means port 3 and 1 are in this vlan. 15 ? 12 0x0 r/w fid specifies the filter id. the ksz8842-pmql/pmbl supports 16 active vlans represented by these four bit fi elds. the fid is the mapped id. if 802.1q vlan is enabled, the look up will be based on fid+da and fid+sa. 11 ? 0 0x001 r/w vid specifies the ieee 802.1q 12 bits vlan id. table 14. vlan table format (16 entries) if 802.1q vlan mode is enabled, ksz8842-pmql/pmbl will assign a vid to every ingress pa cket. if the packet is untagged or tagged with a null vid, the packe t is assigned with the default port vid of the ingress port. if the packet is tagged with non null vid, the vi d in the tag will be used. the look up process will start from the vlan table look up. if the vid is not valid, the packet will be dropped and no addr ess learning will take place. if the vid is valid, the fid is retrieved. the fid+da and fid+sa lookups are performed. the fid+da look up determine s the forwarding ports. if fid+da fails, the packet will be broadcast to all the memb ers (excluding the ingr ess port) of the vlan. if fid+sa fails, the fid+sa will be learned. examples: 1. vlan table read (read the third entry , at the indirect address offset 0x02) write to reg. iacr with 0x1402 (set indirect address and trigger a read vlan table operation) then read reg. iadr5 (vlan table bits 19-16) read reg. iadr4 (vlan table bits 15-0) 2. vlan table write (write the seventh ent ry, at the indirect address offset 0x06) write to reg. iadr5 (vlan table bits 19-16) write to reg. iadr4 (vlan table bits 15-0) write to reg. iacr with 0x1406 (set indirect address and trigger a read vlan table operation)
micrel, inc. ksz8842-pmql/pmbl october 2007 109 m9999-100207-1. 5 absolute maximum ratings (1) supply voltage (v ddatx , v ddarx , v ddio ) ........................... ?0.5v to +4.0v input voltage (all input s). ............................. ?0.5v to +5.0v output voltage (all outpu ts) ......................... ?0.5v to +4.0v lead temperature (solde ring, 10sec .) ....................... 270c storage temperature (t s ) .........................?55c to +150c operating ratings (2) supply voltage (v ddatx , v ddarx , v ddio )...................... +3.1v to +3.5v ambient temp. of mql/mbl(t a )............ 0c to +70c ambient temp. of mqli/mbl am(t a ) . -40c to +85c junction temperature (t j )................................. 125c package thermal resistance (3) pqfp ( ja ) no air fl ow........................ 42.91c/w pqfp ( jc ) no air flow .......................... 19.6c/w lfbga ( ja ) no air flow...................... 38.50c/w lfbga ( jc ) no air flow ...................... 12.50c/w electrical characteristics (4) symbol parameter condition min typ max units supply current 100base-tx operation (all ports @ 100% utilization) i ddxio 100base-tx (analog core + pll + digital core + transceiver + digital i/o) v ddatx , v ddarx , v ddio = 3.3v 122 ma 10base-t operation (all ports @ 100% utilization) i ddxio 100base-t (analog core + pll + digital core + transceiver + digital i/o) v ddatx , v ddarx , v ddio = 3.3v 90 ma ttl inputs v ih input high voltage 2.0 v v il input low voltage 0.8 v i in input current v in = gnd ~ v ddio ?10 10 a ttl outputs v oh output high voltage i oh = ?8ma 2.4 v v ol output low voltage i ol = 8ma 0.4 v i oz output tri-state leakage 10 a 100base-tx transmit (measured differentially after 1:1 transformer) v ddatx = 3.3v only v o peak differential output voltage 100 ? termination on the differential output. 0.95 1.05 v v imb output voltage imbalance 100 ? termination on the differential output. 2 % rise/fall time 3 5 ns rise/fall time imbalance 0 0.5 ns duty cycle distortion 0.5 ns t r , t f overshoot 5 % reference voltage of i set 0.5 v v set output jitter peak to peak 0.7 1.4 ns 10base-t receive v sq squelch threshold 5mhz square wave 400 mv 10base-t transmit (measured differentially after 1:1 transformer) v ddatx = 3.3v only peak differential output voltage 100 ? termination on the differential output. 2.4 v v p jitter added 100 ? termination on the differential output. 1.8 3.5 ns
micrel, inc. ksz8842-pmql/pmbl october 2007 110 m9999-100207-1. 5 notes: 1. exceeding the absolute maximum rating may damage the device. stresses greater than those listed in the table above may cause permanent damage to the device. operation of the device at these or any other conditions above those specif ied in the operating sections of this specification is not implied. maximum conditions for ex tended periods may affect reliability. unused inputs must always be tied to an appropr iate logic voltage level. 2. the device is not guaranteed to function outside its operating rating. unused inputs must always be tied to an appropriate l ogic voltage level (ground to v dd ) 3. no (hs) heat spreader in this pack age. the thermal junction to ambient ( ja ) and the thermal junction to case ( jc ) are under air velocity 0m/s. 4. specification for packaged product only. a single port?s trans former consumes an additional 45m a at 3.3v for 100base-t and 7 0ma at 3.3v for 10base-t.
micrel, inc. ksz8842-pmql/pmbl october 2007 111 m9999-100207-1. 5 timing diagrams for pci timing, please refer to pci specification version 2.2. eeprom timing eecs eesk eedo eedi *1 start bit hight-z d15 d14 d13 d1 d0 11 0 an a0 1 *1 ts th figure 12. eeprom read cycle timing diagram timing parameter description min typ max unit t cyc clock cycle 4000 ns t s setup time 20 ns t h hold time 20 ns table 15. eeprom timing parameters
micrel, inc. ksz8842-pmql/pmbl october 2007 112 m9999-100207-1. 5 auto negotiation timing tx+/tx- tx+/tx- flp burst flp burst t flpw t btb clock pulse clock pulse data pulse data pulse t pw t pw t ctd t ctc figure 13. auto-negotiation timing timing parameter description min typ max unit t btb flp burst to flp burst 8 16 24 ms t flpw flp burst width 2 ms t pw clock/data pulse width 100 ns t ctd clock pulse to data pulse 55.5 64 69.5 s t ctc clock pulse to clock pulse 111 128 139 s number of clock/data pulses per burst 17 33 table 16. auto negotiation parameters
micrel, inc. ksz8842-pmql/pmbl october 2007 113 m9999-100207-1. 5 reset timing as long as the stable supply voltages to reset high timing (minimum of 10ms) are met, there is no power-sequencing requirement for the ksz8842-pmql/pmbl supply voltages 3.3v. the reset timing requirement is summarized in the figure 14 and table 17. supply v oltage rst_n t sr figure 14. reset timing symbol parameter min max unit t sr stable supply voltages to reset high 10 ms table 17. reset timing parameters
micrel, inc. ksz8842-pmql/pmbl october 2007 114 m9999-100207-1. 5 selection of isolation transformers a 1:1 isolation transformer is required at the line interface. an isolation tran sformer with integrated common-mode choke is recommended for exceeding fcc requirements. table 18 gives recommended transformer characteristics. parameter value test condition turns ratio 1 ct : 1 ct open-circuit inductance (min) 350 h 100mv, 100khz, 8ma leakage inductance (max) 0.4 h 1mhz (min) inter-winding capacitance (max) 12pf d.c. resistance (max) 0.9 ? insertion loss (max) 1.0db 0mhz ? 65mhz hipot (min) 1500vrms table 18. transformer selection criteria magnetic manufacturer part number auto mdi-x number of port pulse h1102 yes 1 pulse (low cost) h1260 yes 1 transpower hb726 yes 1 bel fuse s558-5999-u7 yes 1 delta lf8505 yes 1 lankom lf-h41s yes 1 tdk (mag jack) tla-6t718 yes 1 table 19. qualified single port magnetics selection of reference crystal characteristics value units frequency 25 mhz frequency tolerance (max) 50 ppm load capacitance (max) 20 pf series resistance 25 ? table 20. typical reference crystal characteristics
micrel, inc. ksz8842-pmql/pmbl october 2007 115 m9999-100207-1. 5 package information figure 15. 128-pin pqfp
micrel, inc. ksz8842-pmql/pmbl october 2007 116 m9999-100207-1. 5 package information figure 16. 100-ball lfbga
micrel, inc. ksz8842-pmql/pmbl october 2007 117 m9999-100207-1. 5 acronyms and glossary bpdu bridge protocol data unit a packet containing ports, addresses, etc. to make sure data being passed through a bridged network arri ves at its proper destination. cmos complementary metal oxide semiconductor. a common semi conductor manufacturing technique in which positive and negative types of transistors are co mbined to form a current gate that in turn forms an effective means of controlling electrical current through a chip. crc cyclic redundancy check a common technique for detecting data transmission errors . crc for ethernet is 32 bits long. da destination address the address to send packets. dma direct memory access a design in which memory on a chip is controlled independently of the cpu. eisa extended industry standard architecture a bus architecture designed for pcs using 80x86 processors, or an intel 80386, 80486 or pentium mi croprocessor. eisa buses are 32 bits wide and support multiprocessing . emi electro-magnetic interference a naturally oc curring phenomena when the electromagnetic field of one device disrupts, impedes or degrades the electromagnetic field of another device by coming into proximity with it. in computer technology, computer devices are susceptible to emi because electromagnetic fields are a byprod uct of passing electricity through a wire. data lines that have not been properly shielded are susceptible to data corruption by emi. fcs frame check sequence see crc. fid frame or filter id specifies the frame ident ifier. alternately is the filter identifier. ipg inter-packet gap a time delay between su ccessive data packets mandated by the network standard for protocol reas ons. in ethernet, the medium has to be "silent" (i.e., no data transfer) for a short period of time before a node can consider the network idle and start to transmit. ipg is used to correct timing differences between a transmitter and receiver. during the ipg, no data is transferr ed, and information in the gap can be discarded or additions inserted without impact on data integrity. isi inter-symbol interference t he disruption of transmitted code caused by adjacent pulses affecting or interfering with each other. isa industry standard architecture a bus architecture used in the ibm pc/xt and pc/at . mdi medium dependent interface an ethernet port connecti on that allows network hubs or switches to connect to other hubs or switches without a null-modem, or crossover, cable. mdi provides the standard interface to a particular media (copper or fiber) and is therefore 'media dependent.' mdi-x medium dependent interface crossover an ethernet port connection that allows networked end stations (i.e., pcs or workstations) to connect to each other using a null-modem, or crossover, cable. for 10/100 full-duplex networks, an end point (such as a computer) and a switch are wired so that each transmitter connects to the far end receiver. when connecting two computers together, a cable that crosses the tx and rx is required to do this. with auto mdi-x, the phy senses the correct tx and rx roles, eliminating any cable confusion. mib management information base the mib comprises t he management portion of network devices. this can include things like monitoring tr affic levels and faults (statistical),
micrel, inc. ksz8842-pmql/pmbl october 2007 118 m9999-100207-1. 5 and can also change operating parameters in network nodes (static forwarding addresses). mii media independent interface the mii accesses phy registers as defined in the ieee 802.3 specification. nic network interface card an expansion board inserted into a computer to allow it to be connected to a network. most nics are designed for a particular type of network, protocol, and media, although some can serve multiple networks. pll phase-locked loop an electronic circuit that c ontrols an oscillator so that it maintains a constant phase angle (i.e., lock) on the frequency of an input, or reference, signal. a pll ensures that a communication signal is locked on a specific frequency and can also be used to generate, modulate, and demodulate a si gnal and divide a frequency. pme power management event an occurrence that a ffects the directing of power to different components of a system. sa source address the address from which information has been sent. tdr time domain reflectometry tdr is used to pinpoint flaws and problems in underground and aerial wire, cabling, and fiber optics. they send a signal down the conductor and measure the time it ta kes for the signal -- or part of the signal -- to return. utp unshielded twisted pair commonly a cable containing 4 twisted pairs of wires. the wires are twisted in such a manner as to cancel electrical interference generated in each wire, therefore shielding is not required. vlan virtual local area network a configuration of co mputers that acts as if all computers are connected by the same physical network but which may be located virtually anywhere.
micrel, inc. ksz8842-pmql/pmbl october 2007 119 m9999-100207-1. 5 micrel, inc. 2180 fortune drive san jose, ca 95131 usa tel +1 (408) 944-0800 fax +1 (408) 474-1000 web http:/www.micrel.com the information furnished by micrel in this data sheet is belie ved to be accurate and reliable. however, no responsibility is a ssumed by micrel for its use. micrel reserves the right to change circuitry and specificati ons at any time without notification to the customer. micrel products are not designed or authori zed for use as components in life support app liances, devices or systems where malfu nction of a product can reasonably be expected to result in personal injury. li fe support devices or systems are devices or systems that (a ) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to resul t in a significant injury to the user. a purchaser?s use or sale of micrel products for use in life s upport appliances, devices or systems is a pu rchaser?s own risk and purchaser agrees to fully indemnify micrel fo r any damages resulting from such use or sale. ? 2007 micrel, incorporated.

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